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radeonsi: si_conv_pipe_prim shouldn't fail

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An assertion should suffice.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Marek Olšák
2014-12-07 16:02:07 +01:00
parent c6546cfb03
commit 508c1ca6af
1 changed files with 3 additions and 11 deletions
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src/gallium/drivers/radeonsi/si_state_draw.c
+3 -11
View File
@@ -341,7 +341,7 @@ void si_shader_init_pm4_state(struct si_shader *shader)
* Drawing
*/
static unsigned si_conv_pipe_prim(unsigned pprim)
static unsigned si_conv_pipe_prim(unsigned mode)
{
static const unsigned prim_conv[] = {
[PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
@@ -360,11 +360,8 @@ static unsigned si_conv_pipe_prim(unsigned pprim)
[PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
[R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
};
unsigned result = prim_conv[pprim];
if (result == ~0) {
R600_ERR("unsupported primitive type %d\n", pprim);
}
return result;
assert(mode < Elements(prim_conv));
return prim_conv[mode];
}
static unsigned si_conv_prim_to_gs_out(unsigned mode)
@@ -465,11 +462,6 @@ static bool si_update_draw_info_state(struct si_context *sctx,
if (pm4 == NULL)
return false;
if (prim == ~0) {
FREE(pm4);
return false;
}
if (sctx->b.chip_class >= CIK) {
si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
ib->index_size == 4 ? 0xFC000000 : 0xFC00);