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i965: Eliminate all tabs except in brw_defines.h

Browse Source 
For a while we were doing 3-space indent with 8-space tabs, largely
due to the emacs settings of a couple of contributors.  We stopped
using tabs a long time ago, and they're just a nuisance at this point.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9207>
This commit is contained in:
Kenneth Graunke
2021-02-22 19:04:39 -08:00
committed by Marge Bot
parent 95bd5fc463
commit 5005cbc7ed
39 changed files with 514 additions and 514 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/mesa/drivers/dri/i965/brw_clear.c
+5 -5
View File
@@ -66,8 +66,8 @@ debug_mask(const char *name, GLbitfield mask)
if (INTEL_DEBUG & DEBUG_BLIT) {
DBG("%s clear:", name);
for (i = 0; i < BUFFER_COUNT; i++) {
if (mask & (1 << i))
DBG(" %s", buffer_names[i]);
if (mask & (1 << i))
DBG(" %s", buffer_names[i]);
}
DBG("\n");
}
@@ -155,7 +155,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
if (devinfo->gen == 6 &&
(minify(mt->surf.phys_level0_sa.width,
depth_irb->mt_level - mt->first_level) % 16) != 0)
return false;
return false;
break;
default:
@@ -258,8 +258,8 @@ brw_clear(struct gl_context *ctx, GLbitfield mask)
if (mask & BUFFER_BIT_DEPTH) {
if (brw_fast_clear_depth(ctx)) {
DBG("fast clear: depth\n");
mask &= ~BUFFER_BIT_DEPTH;
DBG("fast clear: depth\n");
mask &= ~BUFFER_BIT_DEPTH;
}
}
src/mesa/drivers/dri/i965/brw_clip.c
+78 -78
View File
@@ -42,8 +42,8 @@
#include "util/ralloc.h"
static void compile_clip_prog( struct brw_context *brw,
struct brw_clip_prog_key *key )
static void
compile_clip_prog(struct brw_context *brw, struct brw_clip_prog_key *key)
{
const unsigned *program;
void *mem_ctx;
@@ -56,11 +56,11 @@ static void compile_clip_prog( struct brw_context *brw,
&brw->vue_map_geom_out, &program_size);
brw_upload_cache(&brw->cache,
BRW_CACHE_CLIP_PROG,
key, sizeof(*key),
program, program_size,
&prog_data, sizeof(prog_data),
&brw->clip.prog_offset, &brw->clip.prog_data);
BRW_CACHE_CLIP_PROG,
key, sizeof(*key),
program, program_size,
&prog_data, sizeof(prog_data),
&brw->clip.prog_offset, &brw->clip.prog_data);
ralloc_free(mem_ctx);
}
@@ -122,84 +122,84 @@ brw_upload_clip_prog(struct brw_context *brw)
/* _NEW_POLYGON */
if (key.primitive == GL_TRIANGLES) {
if (ctx->Polygon.CullFlag &&
ctx->Polygon.CullFaceMode == GL_FRONT_AND_BACK)
key.clip_mode = BRW_CLIP_MODE_REJECT_ALL;
ctx->Polygon.CullFaceMode == GL_FRONT_AND_BACK)
key.clip_mode = BRW_CLIP_MODE_REJECT_ALL;
else {
GLuint fill_front = BRW_CLIP_FILL_MODE_CULL;
GLuint fill_back = BRW_CLIP_FILL_MODE_CULL;
GLuint offset_front = 0;
GLuint offset_back = 0;
GLuint fill_front = BRW_CLIP_FILL_MODE_CULL;
GLuint fill_back = BRW_CLIP_FILL_MODE_CULL;
GLuint offset_front = 0;
GLuint offset_back = 0;
if (!ctx->Polygon.CullFlag ||
ctx->Polygon.CullFaceMode != GL_FRONT) {
switch (ctx->Polygon.FrontMode) {
case GL_FILL:
fill_front = BRW_CLIP_FILL_MODE_FILL;
offset_front = 0;
break;
case GL_LINE:
fill_front = BRW_CLIP_FILL_MODE_LINE;
offset_front = ctx->Polygon.OffsetLine;
break;
case GL_POINT:
fill_front = BRW_CLIP_FILL_MODE_POINT;
offset_front = ctx->Polygon.OffsetPoint;
break;
}
}
if (!ctx->Polygon.CullFlag ||
ctx->Polygon.CullFaceMode != GL_FRONT) {
switch (ctx->Polygon.FrontMode) {
case GL_FILL:
fill_front = BRW_CLIP_FILL_MODE_FILL;
offset_front = 0;
break;
case GL_LINE:
fill_front = BRW_CLIP_FILL_MODE_LINE;
offset_front = ctx->Polygon.OffsetLine;
break;
case GL_POINT:
fill_front = BRW_CLIP_FILL_MODE_POINT;
offset_front = ctx->Polygon.OffsetPoint;
break;
}
}
if (!ctx->Polygon.CullFlag ||
ctx->Polygon.CullFaceMode != GL_BACK) {
switch (ctx->Polygon.BackMode) {
case GL_FILL:
fill_back = BRW_CLIP_FILL_MODE_FILL;
offset_back = 0;
break;
case GL_LINE:
fill_back = BRW_CLIP_FILL_MODE_LINE;
offset_back = ctx->Polygon.OffsetLine;
break;
case GL_POINT:
fill_back = BRW_CLIP_FILL_MODE_POINT;
offset_back = ctx->Polygon.OffsetPoint;
break;
}
}
if (!ctx->Polygon.CullFlag ||
ctx->Polygon.CullFaceMode != GL_BACK) {
switch (ctx->Polygon.BackMode) {
case GL_FILL:
fill_back = BRW_CLIP_FILL_MODE_FILL;
offset_back = 0;
break;
case GL_LINE:
fill_back = BRW_CLIP_FILL_MODE_LINE;
offset_back = ctx->Polygon.OffsetLine;
break;
case GL_POINT:
fill_back = BRW_CLIP_FILL_MODE_POINT;
offset_back = ctx->Polygon.OffsetPoint;
break;
}
}
if (ctx->Polygon.BackMode != GL_FILL ||
ctx->Polygon.FrontMode != GL_FILL) {
key.do_unfilled = 1;
if (ctx->Polygon.BackMode != GL_FILL ||
ctx->Polygon.FrontMode != GL_FILL) {
key.do_unfilled = 1;
/* Most cases the fixed function units will handle. Cases where
* one or more polygon faces are unfilled will require help:
*/
key.clip_mode = BRW_CLIP_MODE_CLIP_NON_REJECTED;
/* Most cases the fixed function units will handle. Cases where
* one or more polygon faces are unfilled will require help:
*/
key.clip_mode = BRW_CLIP_MODE_CLIP_NON_REJECTED;
if (offset_back || offset_front) {
/* _NEW_POLYGON, _NEW_BUFFERS */
key.offset_units = ctx->Polygon.OffsetUnits * ctx->DrawBuffer->_MRD * 2;
key.offset_factor = ctx->Polygon.OffsetFactor * ctx->DrawBuffer->_MRD;
key.offset_clamp = ctx->Polygon.OffsetClamp * ctx->DrawBuffer->_MRD;
}
if (offset_back || offset_front) {
/* _NEW_POLYGON, _NEW_BUFFERS */
key.offset_units = ctx->Polygon.OffsetUnits * ctx->DrawBuffer->_MRD * 2;
key.offset_factor = ctx->Polygon.OffsetFactor * ctx->DrawBuffer->_MRD;
key.offset_clamp = ctx->Polygon.OffsetClamp * ctx->DrawBuffer->_MRD;
}
if (!brw->polygon_front_bit) {
key.fill_ccw = fill_front;
key.fill_cw = fill_back;
key.offset_ccw = offset_front;
key.offset_cw = offset_back;
if (ctx->Light.Model.TwoSide &&
key.fill_cw != BRW_CLIP_FILL_MODE_CULL)
key.copy_bfc_cw = 1;
} else {
key.fill_cw = fill_front;
key.fill_ccw = fill_back;
key.offset_cw = offset_front;
key.offset_ccw = offset_back;
if (ctx->Light.Model.TwoSide &&
key.fill_ccw != BRW_CLIP_FILL_MODE_CULL)
key.copy_bfc_ccw = 1;
}
}
if (!brw->polygon_front_bit) {
key.fill_ccw = fill_front;
key.fill_cw = fill_back;
key.offset_ccw = offset_front;
key.offset_cw = offset_back;
if (ctx->Light.Model.TwoSide &&
key.fill_cw != BRW_CLIP_FILL_MODE_CULL)
key.copy_bfc_cw = 1;
} else {
key.fill_cw = fill_front;
key.fill_ccw = fill_back;
key.offset_cw = offset_front;
key.offset_ccw = offset_back;
if (ctx->Light.Model.TwoSide &&
key.fill_ccw != BRW_CLIP_FILL_MODE_CULL)
key.copy_bfc_ccw = 1;
}
}
}
}
src/mesa/drivers/dri/i965/brw_context.c
+7 -7
View File
@@ -646,7 +646,7 @@ brw_initialize_context_constants(struct brw_context *brw)
ctx->Const.Program[MESA_SHADER_VERTEX].MaxNativeParameters = 1024;
ctx->Const.Program[MESA_SHADER_VERTEX].MaxEnvParams =
MIN2(ctx->Const.Program[MESA_SHADER_VERTEX].MaxNativeParameters,
ctx->Const.Program[MESA_SHADER_VERTEX].MaxEnvParams);
ctx->Const.Program[MESA_SHADER_VERTEX].MaxEnvParams);
ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxNativeInstructions = 1024;
ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxNativeAluInstructions = 1024;
@@ -658,7 +658,7 @@ brw_initialize_context_constants(struct brw_context *brw)
ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxNativeParameters = 1024;
ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxEnvParams =
MIN2(ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxNativeParameters,
ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxEnvParams);
ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxEnvParams);
/* Fragment shaders use real, 32-bit twos-complement integers for all
* integer types.
@@ -1086,7 +1086,7 @@ brw_create_context(gl_api api,
if (hw_priority != I915_CONTEXT_DEFAULT_PRIORITY &&
brw_hw_context_set_priority(brw->bufmgr, brw->hw_ctx, hw_priority)) {
fprintf(stderr,
"Failed to set priority [%d:%d] for hardware context.\n",
"Failed to set priority [%d:%d] for hardware context.\n",
ctx_config->priority, hw_priority);
brw_destroy_context(driContextPriv);
return false;
@@ -1699,10 +1699,10 @@ brw_process_dri2_buffer(struct brw_context *brw,
uint32_t old_name = 0;
if (last_mt) {
/* The bo already has a name because the miptree was created by a
* previous call to brw_process_dri2_buffer(). If a bo already has a
* name, then brw_bo_flink() is a low-cost getter. It does not
* create a new name.
*/
* previous call to brw_process_dri2_buffer(). If a bo already has a
* name, then brw_bo_flink() is a low-cost getter. It does not
* create a new name.
*/
brw_bo_flink(last_mt->bo, &old_name);
}
src/mesa/drivers/dri/i965/brw_context.h
+9 -9
View File
@@ -1012,12 +1012,12 @@ struct brw_context
/* BRW_NEW_URB_ALLOCATIONS:
*/
struct {
GLuint vsize; /* vertex size plus header in urb registers */
GLuint gsize; /* GS output size in urb registers */
GLuint hsize; /* Tessellation control output size in urb registers */
GLuint dsize; /* Tessellation evaluation output size in urb registers */
GLuint csize; /* constant buffer size in urb registers */
GLuint sfsize; /* setup data size in urb registers */
GLuint vsize; /* vertex size plus header in urb registers */
GLuint gsize; /* GS output size in urb registers */
GLuint hsize; /* Tessellation control output size in urb registers */
GLuint dsize; /* Tessellation evaluation output size in urb registers */
GLuint csize; /* constant buffer size in urb registers */
GLuint sfsize; /* setup data size in urb registers */
bool constrained;
@@ -1366,7 +1366,7 @@ void brw_validate_textures( struct brw_context *brw );
void brw_init_frag_prog_functions(struct dd_function_table *functions);
void brw_get_scratch_bo(struct brw_context *brw,
struct brw_bo **scratch_bo, int size);
struct brw_bo **scratch_bo, int size);
void brw_alloc_stage_scratch(struct brw_context *brw,
struct brw_stage_state *stage_state,
unsigned per_thread_size);
@@ -1452,7 +1452,7 @@ brw_delete_transform_feedback(struct gl_context *ctx,
struct gl_transform_feedback_object *obj);
void
brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
struct gl_transform_feedback_object *obj);
struct gl_transform_feedback_object *obj);
void
brw_end_transform_feedback(struct gl_context *ctx,
struct gl_transform_feedback_object *obj);
@@ -1476,7 +1476,7 @@ gen7_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
struct gl_transform_feedback_object *obj);
void
gen7_end_transform_feedback(struct gl_context *ctx,
struct gl_transform_feedback_object *obj);
struct gl_transform_feedback_object *obj);
void
gen7_pause_transform_feedback(struct gl_context *ctx,
struct gl_transform_feedback_object *obj);
src/mesa/drivers/dri/i965/brw_curbe.c
+8 -8
View File
@@ -112,7 +112,7 @@ static void calculate_curbe_offsets( struct brw_context *brw )
nr_vp_regs > brw->curbe.vs_size ||
nr_clip_regs != brw->curbe.clip_size ||
(total_regs < brw->curbe.total_size / 4 &&
brw->curbe.total_size > 16)) {
brw->curbe.total_size > 16)) {
GLuint reg = 0;
@@ -128,7 +128,7 @@ static void calculate_curbe_offsets( struct brw_context *brw )
brw->curbe.total_size = reg;
if (0)
fprintf(stderr, "curbe wm %d+%d clip %d+%d vs %d+%d\n",
fprintf(stderr, "curbe wm %d+%d clip %d+%d vs %d+%d\n",
brw->curbe.wm_start,
brw->curbe.wm_size,
brw->curbe.clip_start,
@@ -241,10 +241,10 @@ brw_upload_constant_buffer(struct brw_context *brw)
/* If any planes are going this way, send them all this way:
*/
for (i = 0; i < 6; i++) {
buf[offset + i * 4 + 0].f = fixed_plane[i][0];
buf[offset + i * 4 + 1].f = fixed_plane[i][1];
buf[offset + i * 4 + 2].f = fixed_plane[i][2];
buf[offset + i * 4 + 3].f = fixed_plane[i][3];
buf[offset + i * 4 + 0].f = fixed_plane[i][0];
buf[offset + i * 4 + 1].f = fixed_plane[i][1];
buf[offset + i * 4 + 2].f = fixed_plane[i][2];
buf[offset + i * 4 + 3].f = fixed_plane[i][3];
}
/* Clip planes: _NEW_TRANSFORM plus _NEW_PROJECTION to get to
@@ -276,7 +276,7 @@ brw_upload_constant_buffer(struct brw_context *brw)
if (0) {
for (i = 0; i < sz*16; i+=4)
fprintf(stderr, "curbe %d.%d: %f %f %f %f\n", i/8, i&4,
fprintf(stderr, "curbe %d.%d: %f %f %f %f\n", i/8, i&4,
buf[i+0].f, buf[i+1].f, buf[i+2].f, buf[i+3].f);
}
@@ -310,7 +310,7 @@ emit:
} else {
OUT_BATCH((CMD_CONST_BUFFER << 16) | (1 << 8) | (2 - 2));
OUT_RELOC(brw->curbe.curbe_bo, 0,
(brw->curbe.total_size - 1) + brw->curbe.curbe_offset);
(brw->curbe.total_size - 1) + brw->curbe.curbe_offset);
}
ADVANCE_BATCH();
src/mesa/drivers/dri/i965/brw_draw.c
+2 -2
View File
@@ -536,10 +536,10 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering,
/* Resolve depth buffer and render cache of each enabled texture. */
for (int i = 0; i <= maxEnabledUnit; i++) {
if (!ctx->Texture.Unit[i]._Current)
continue;
continue;
tex_obj = brw_texture_object(ctx->Texture.Unit[i]._Current);
if (!tex_obj || !tex_obj->mt)
continue;
continue;
struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, i);
enum isl_format view_format =
src/mesa/drivers/dri/i965/brw_draw.h
+11 -11
View File
@@ -26,7 +26,7 @@
#ifndef BRW_DRAW_H
#define BRW_DRAW_H
#include "main/mtypes.h" /* for struct gl_context... */
#include "main/mtypes.h"
#include "brw_bufmgr.h"
struct brw_context;
@@ -45,16 +45,16 @@ brw_emit_vertex_buffer_state(struct brw_context *brw,
brw_emit_vertex_buffer_state(__VA_ARGS__, __map)
void brw_draw_prims(struct gl_context *ctx,
const struct _mesa_prim *prims,
unsigned nr_prims,
const struct _mesa_index_buffer *ib,
bool index_bounds_valid,
bool primitive_restart,
unsigned restart_index,
unsigned min_index,
unsigned max_index,
unsigned num_instances,
unsigned base_instance);
const struct _mesa_prim *prims,
unsigned nr_prims,
const struct _mesa_index_buffer *ib,
bool index_bounds_valid,
bool primitive_restart,
unsigned restart_index,
unsigned min_index,
unsigned max_index,
unsigned num_instances,
unsigned base_instance);
void brw_init_draw_functions(struct dd_function_table *functions);
void brw_draw_init( struct brw_context *brw );
src/mesa/drivers/dri/i965/brw_draw_upload.c
+3 -3
View File
@@ -401,9 +401,9 @@ brw_get_vertex_surface_type(struct brw_context *brw,
static void
copy_array_to_vbo_array(struct brw_context *brw,
const uint8_t *const ptr, const int src_stride,
int min, int max,
struct brw_vertex_buffer *buffer,
GLuint dst_stride)
int min, int max,
struct brw_vertex_buffer *buffer,
GLuint dst_stride)
{
const unsigned char *src = ptr + min * src_stride;
int count = max - min + 1;
src/mesa/drivers/dri/i965/brw_ff_gs.c
+16 -16
View File
@@ -82,18 +82,18 @@ brw_codegen_ff_gs_prog(struct brw_context *brw,
case _3DPRIM_POINTLIST:
num_verts = 1;
check_edge_flag = false;
break;
break;
case _3DPRIM_LINELIST:
case _3DPRIM_LINESTRIP:
case _3DPRIM_LINELOOP:
num_verts = 2;
check_edge_flag = false;
break;
break;
case _3DPRIM_TRILIST:
case _3DPRIM_TRIFAN:
case _3DPRIM_TRISTRIP:
case _3DPRIM_RECTLIST:
num_verts = 3;
num_verts = 3;
check_edge_flag = false;
break;
case _3DPRIM_QUADLIST:
@@ -103,7 +103,7 @@ brw_codegen_ff_gs_prog(struct brw_context *brw,
check_edge_flag = true;
break;
default:
unreachable("Unexpected primitive type in Gen6 SOL program.");
unreachable("Unexpected primitive type in Gen6 SOL program.");
}
gen6_sol_program(&c, key, num_verts, check_edge_flag);
} else {
@@ -113,17 +113,17 @@ brw_codegen_ff_gs_prog(struct brw_context *brw,
*/
switch (key->primitive) {
case _3DPRIM_QUADLIST:
brw_ff_gs_quads( &c, key );
break;
brw_ff_gs_quads( &c, key );
break;
case _3DPRIM_QUADSTRIP:
brw_ff_gs_quad_strip( &c, key );
break;
brw_ff_gs_quad_strip( &c, key );
break;
case _3DPRIM_LINELOOP:
brw_ff_gs_lines( &c );
break;
brw_ff_gs_lines( &c );
break;
default:
ralloc_free(mem_ctx);
return;
ralloc_free(mem_ctx);
return;
}
}
@@ -141,10 +141,10 @@ brw_codegen_ff_gs_prog(struct brw_context *brw,
}
brw_upload_cache(&brw->cache, BRW_CACHE_FF_GS_PROG,
&c.key, sizeof(c.key),
program, program_size,
&c.prog_data, sizeof(c.prog_data),
&brw->ff_gs.prog_offset, &brw->ff_gs.prog_data);
&c.key, sizeof(c.key),
program, program_size,
&c.prog_data, sizeof(c.prog_data),
&brw->ff_gs.prog_offset, &brw->ff_gs.prog_data);
ralloc_free(mem_ctx);
}
src/mesa/drivers/dri/i965/brw_ff_gs_emit.c
+4 -4
View File
@@ -335,7 +335,7 @@ void brw_ff_gs_lines(struct brw_ff_gs_compile *c)
*/
void
gen6_sol_program(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key,
unsigned num_verts, bool check_edge_flags)
unsigned num_verts, bool check_edge_flags)
{
struct brw_codegen *p = &c->func;
brw_inst *inst;
@@ -358,10 +358,10 @@ gen6_sol_program(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key,
* Make sure that the buffers have enough room for all the vertices.
*/
brw_ADD(p, get_element_ud(c->reg.temp, 0),
get_element_ud(c->reg.SVBI, 0), brw_imm_ud(num_verts));
get_element_ud(c->reg.SVBI, 0), brw_imm_ud(num_verts));
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_LE,
get_element_ud(c->reg.temp, 0),
get_element_ud(c->reg.SVBI, 4));
get_element_ud(c->reg.temp, 0),
get_element_ud(c->reg.SVBI, 4));
brw_IF(p, BRW_EXECUTE_1);
/* Compute the destination indices to write to. Usually we use SVBI[0]
src/mesa/drivers/dri/i965/brw_misc_state.c
+17 -17
View File
@@ -112,7 +112,7 @@ brw_depthbuffer_format(struct brw_context *brw)
(srb = brw_get_renderbuffer(fb, BUFFER_STENCIL)) &&
!srb->mt->stencil_mt &&
(brw_rb_format(srb) == MESA_FORMAT_Z24_UNORM_S8_UINT ||
brw_rb_format(srb) == MESA_FORMAT_Z32_FLOAT_S8X24_UINT)) {
brw_rb_format(srb) == MESA_FORMAT_Z32_FLOAT_S8X24_UINT)) {
drb = srb;
}
@@ -838,20 +838,20 @@ brw_upload_state_base_address(struct brw_context *brw)
mocs << 4 | /* Stateless Data Port Access Memory Object Control State */
1); /* General State Base Address Modify Enable */
/* Surface state base address:
* BINDING_TABLE_STATE
* SURFACE_STATE
*/
* BINDING_TABLE_STATE
* SURFACE_STATE
*/
OUT_RELOC(brw->batch.state.bo, 0, 1);
/* Dynamic state base address:
* SAMPLER_STATE
* SAMPLER_BORDER_COLOR_STATE
* CLIP, SF, WM/CC viewport state
* COLOR_CALC_STATE
* DEPTH_STENCIL_STATE
* BLEND_STATE
* Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
* Disable is clear, which we rely on)
*/
* SAMPLER_STATE
* SAMPLER_BORDER_COLOR_STATE
* CLIP, SF, WM/CC viewport state
* COLOR_CALC_STATE
* DEPTH_STENCIL_STATE
* BLEND_STATE
* Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
* Disable is clear, which we rely on)
*/
OUT_RELOC(brw->batch.state.bo, 0, 1);
OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
@@ -861,10 +861,10 @@ brw_upload_state_base_address(struct brw_context *brw)
OUT_BATCH(1); /* General state upper bound */
/* Dynamic state upper bound. Although the documentation says that
* programming it to zero will cause it to be ignored, that is a lie.
* If this isn't programmed to a real bound, the sampler border color
* pointer is rejected, causing border color to mysteriously fail.
*/
* programming it to zero will cause it to be ignored, that is a lie.
* If this isn't programmed to a real bound, the sampler border color
* pointer is rejected, causing border color to mysteriously fail.
*/
OUT_BATCH(0xfffff001);
OUT_BATCH(1); /* Indirect object upper bound */
OUT_BATCH(1); /* Instruction access upper bound */
src/mesa/drivers/dri/i965/brw_pipe_control.h
+1 -1
View File
@@ -77,7 +77,7 @@ enum pipe_control_flags
/** @} */
int brw_init_pipe_control(struct brw_context *brw,
const struct gen_device_info *info);
const struct gen_device_info *info);
void brw_fini_pipe_control(struct brw_context *brw);
void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags);
src/mesa/drivers/dri/i965/brw_program.c
+4 -4
View File
@@ -291,7 +291,7 @@ brw_program_string_notify(struct gl_context *ctx,
brw_program_const(brw->programs[MESA_SHADER_FRAGMENT]);
if (newFP == curFP)
brw->ctx.NewDriverState |= BRW_NEW_FRAGMENT_PROGRAM;
brw->ctx.NewDriverState |= BRW_NEW_FRAGMENT_PROGRAM;
_mesa_program_fragment_position_to_sysval(&newFP->program);
newFP->id = get_new_program_id(brw->screen);
@@ -310,9 +310,9 @@ brw_program_string_notify(struct gl_context *ctx,
brw_program_const(brw->programs[MESA_SHADER_VERTEX]);
if (newVP == curVP)
brw->ctx.NewDriverState |= BRW_NEW_VERTEX_PROGRAM;
brw->ctx.NewDriverState |= BRW_NEW_VERTEX_PROGRAM;
if (newVP->program.arb.IsPositionInvariant) {
_mesa_insert_mvp_code(ctx, &newVP->program);
_mesa_insert_mvp_code(ctx, &newVP->program);
}
newVP->id = get_new_program_id(brw->screen);
@@ -404,7 +404,7 @@ brw_framebuffer_fetch_barrier(struct gl_context *ctx)
void
brw_get_scratch_bo(struct brw_context *brw,
struct brw_bo **scratch_bo, int size)
struct brw_bo **scratch_bo, int size)
{
struct brw_bo *old_bo = *scratch_bo;
src/mesa/drivers/dri/i965/brw_queryobj.c
+7 -8
View File
@@ -123,7 +123,7 @@ brw_write_depth_count(struct brw_context *brw, struct brw_bo *query_bo, int idx)
*/
static void
brw_queryobj_get_results(struct gl_context *ctx,
struct brw_query_object *query)
struct brw_query_object *query)
{
struct brw_context *brw = brw_context(ctx);
UNUSED const struct gen_device_info *devinfo = &brw->screen->devinfo;
@@ -181,7 +181,7 @@ brw_queryobj_get_results(struct gl_context *ctx,
* this function was already called to accumulate the results so far.
*/
for (i = 0; i < query->last_index; i++) {
query->Base.Result += results[i * 2 + 1] - results[i * 2];
query->Base.Result += results[i * 2 + 1] - results[i * 2];
}
break;
@@ -191,7 +191,7 @@ brw_queryobj_get_results(struct gl_context *ctx,
* differ, then some fragments passed the depth test.
*/
for (i = 0; i < query->last_index; i++) {
if (results[i * 2 + 1] != results[i * 2]) {
if (results[i * 2 + 1] != results[i * 2]) {
query->Base.Result = GL_TRUE;
break;
}
@@ -345,12 +345,11 @@ brw_end_query(struct gl_context *ctx, struct gl_query_object *q)
* case, we emit the query_begin and query_end state to the
* hardware. This is to guarantee that waiting on the result of this
* empty state will cause all previous queries to complete at all, as
* required by the specification:
* required by the OpenGL 4.3 (Core Profile) spec, section 4.2.1:
*
* It must always be true that if any query object
* returns a result available of TRUE, all queries of the
* same type issued prior to that query must also return
* TRUE. [Open GL 4.3 (Core Profile) Section 4.2.1]
* "It must always be true that if any query object returns
* a result available of TRUE, all queries of the same type
* issued prior to that query must also return TRUE."
*/
if (!query->bo) {
brw_emit_query_begin(brw);
src/mesa/drivers/dri/i965/brw_sf.c
+8 -8
View File
@@ -46,8 +46,8 @@
#include "util/ralloc.h"
static void compile_sf_prog( struct brw_context *brw,
struct brw_sf_prog_key *key )
static void
compile_sf_prog(struct brw_context *brw, struct brw_sf_prog_key *key)
{
const unsigned *program;
void *mem_ctx;
@@ -60,10 +60,10 @@ static void compile_sf_prog( struct brw_context *brw,
&brw->vue_map_geom_out, &program_size);
brw_upload_cache(&brw->cache, BRW_CACHE_SF_PROG,
key, sizeof(*key),
program, program_size,
&prog_data, sizeof(prog_data),
&brw->sf.prog_offset, &brw->sf.prog_data);
key, sizeof(*key),
program, program_size,
&prog_data, sizeof(prog_data),
&brw->sf.prog_offset, &brw->sf.prog_data);
ralloc_free(mem_ctx);
}
@@ -108,9 +108,9 @@ brw_upload_sf_prog(struct brw_context *brw)
* program.
*/
if (key.attrs & BITFIELD64_BIT(VARYING_SLOT_EDGE))
key.primitive = BRW_SF_PRIM_UNFILLED_TRIS;
key.primitive = BRW_SF_PRIM_UNFILLED_TRIS;
else
key.primitive = BRW_SF_PRIM_TRIANGLES;
key.primitive = BRW_SF_PRIM_TRIANGLES;
break;
case GL_LINES:
key.primitive = BRW_SF_PRIM_LINES;
src/mesa/drivers/dri/i965/brw_state_upload.c
+21 -20
View File
@@ -372,17 +372,18 @@ check_state(const struct brw_state_flags *a, const struct brw_state_flags *b)
return ((a->mesa & b->mesa) | (a->brw & b->brw)) != 0;
}
static void accumulate_state( struct brw_state_flags *a,
const struct brw_state_flags *b )
static void
accumulate_state(struct brw_state_flags *a, const struct brw_state_flags *b)
{
a->mesa |= b->mesa;
a->brw |= b->brw;
}
static void xor_states( struct brw_state_flags *result,
const struct brw_state_flags *a,
const struct brw_state_flags *b )
static void
xor_states(struct brw_state_flags *result,
const struct brw_state_flags *a,
const struct brw_state_flags *b)
{
result->mesa = a->mesa ^ b->mesa;
result->brw = a->brw ^ b->brw;
@@ -496,7 +497,7 @@ brw_update_dirty_count(struct dirty_bit_map *bit_map, uint64_t bits)
{
for (int i = 0; bit_map[i].bit != 0; i++) {
if (bit_map[i].bit & bits)
bit_map[i].count++;
bit_map[i].count++;
}
}
@@ -700,25 +701,25 @@ brw_upload_pipeline_state(struct brw_context *brw,
prev = state;
for (i = 0; i < num_atoms; i++) {
const struct brw_tracked_state *atom = &atoms[i];
struct brw_state_flags generated;
const struct brw_tracked_state *atom = &atoms[i];
struct brw_state_flags generated;
check_and_emit_atom(brw, &state, atom);
accumulate_state(&examined, &atom->dirty);
accumulate_state(&examined, &atom->dirty);
/* generated = (prev ^ state)
* if (examined & generated)
* fail;
*/
xor_states(&generated, &prev, &state);
assert(!check_state(&examined, &generated));
prev = state;
/* generated = (prev ^ state)
* if (examined & generated)
* fail;
*/
xor_states(&generated, &prev, &state);
assert(!check_state(&examined, &generated));
prev = state;
}
}
else {
for (i = 0; i < num_atoms; i++) {
const struct brw_tracked_state *atom = &atoms[i];
const struct brw_tracked_state *atom = &atoms[i];
check_and_emit_atom(brw, &state, atom);
}
@@ -730,9 +731,9 @@ brw_upload_pipeline_state(struct brw_context *brw,
brw_update_dirty_count(mesa_bits, state.mesa);
brw_update_dirty_count(brw_bits, state.brw);
if (dirty_count++ % 1000 == 0) {
brw_print_dirty_count(mesa_bits);
brw_print_dirty_count(brw_bits);
fprintf(stderr, "\n");
brw_print_dirty_count(mesa_bits);
brw_print_dirty_count(brw_bits);
fprintf(stderr, "\n");
}
}
}
src/mesa/drivers/dri/i965/brw_surface_formats.c
+22 -22
View File
@@ -225,7 +225,7 @@ brw_screen_init_surface_formats(struct brw_screen *screen)
render = texture = brw_isl_format_for_mesa_format(format);
if (texture == ISL_FORMAT_UNSUPPORTED)
continue;
continue;
/* Don't advertise 8 and 16-bit RGB formats to core mesa. This ensures
* that they are renderable from an API perspective since core mesa will
@@ -239,24 +239,24 @@ brw_screen_init_surface_formats(struct brw_screen *screen)
if (isl_format_supports_sampling(devinfo, texture) &&
(isl_format_supports_filtering(devinfo, texture) || is_integer))
screen->mesa_format_supports_texture[format] = true;
screen->mesa_format_supports_texture[format] = true;
/* Re-map some render target formats to make them supported when they
* wouldn't be using their format for texturing.
*/
switch (render) {
/* For these formats, we just need to read/write the first
* channel into R, which is to say that we just treat them as
* GL_RED.
*/
/* For these formats, we just need to read/write the first
* channel into R, which is to say that we just treat them as
* GL_RED.
*/
case ISL_FORMAT_I32_FLOAT:
case ISL_FORMAT_L32_FLOAT:
render = ISL_FORMAT_R32_FLOAT;
break;
render = ISL_FORMAT_R32_FLOAT;
break;
case ISL_FORMAT_I16_FLOAT:
case ISL_FORMAT_L16_FLOAT:
render = ISL_FORMAT_R16_FLOAT;
break;
render = ISL_FORMAT_R16_FLOAT;
break;
case ISL_FORMAT_I8_UNORM:
case ISL_FORMAT_L8_UNORM:
render = ISL_FORMAT_R8_UNORM;
@@ -272,16 +272,16 @@ brw_screen_init_surface_formats(struct brw_screen *screen)
render = ISL_FORMAT_R16G16B16A16_FLOAT;
break;
case ISL_FORMAT_B8G8R8X8_UNORM:
/* XRGB is handled as ARGB because the chips in this family
* cannot render to XRGB targets. This means that we have to
* mask writes to alpha (ala glColorMask) and reconfigure the
* alpha blending hardware to use GL_ONE (or GL_ZERO) for
* cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
* used. On Gen8+ BGRX is actually allowed (but not RGBX).
*/
/* XRGB is handled as ARGB because the chips in this family
* cannot render to XRGB targets. This means that we have to
* mask writes to alpha (ala glColorMask) and reconfigure the
* alpha blending hardware to use GL_ONE (or GL_ZERO) for
* cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
* used. On Gen8+ BGRX is actually allowed (but not RGBX).
*/
if (!isl_format_supports_rendering(devinfo, texture))
render = ISL_FORMAT_B8G8R8A8_UNORM;
break;
break;
case ISL_FORMAT_B8G8R8X8_UNORM_SRGB:
if (!isl_format_supports_rendering(devinfo, texture))
render = ISL_FORMAT_B8G8R8A8_UNORM_SRGB;
@@ -303,8 +303,8 @@ brw_screen_init_surface_formats(struct brw_screen *screen)
*/
if (isl_format_supports_rendering(devinfo, render) &&
(isl_format_supports_alpha_blending(devinfo, render) || is_integer)) {
screen->mesa_to_isl_render_format[format] = render;
screen->mesa_format_supports_render[format] = true;
screen->mesa_to_isl_render_format[format] = render;
screen->mesa_format_supports_render[format] = true;
}
}
@@ -413,7 +413,7 @@ brw_init_surface_formats(struct brw_context *brw)
bool
brw_render_target_supported(struct brw_context *brw,
struct gl_renderbuffer *rb)
struct gl_renderbuffer *rb)
{
const struct gen_device_info *devinfo = &brw->screen->devinfo;
mesa_format format = rb->Format;
@@ -450,7 +450,7 @@ brw_render_target_supported(struct brw_context *brw,
enum isl_format
translate_tex_format(struct brw_context *brw,
mesa_format mesa_format,
GLenum srgb_decode)
GLenum srgb_decode)
{
struct gl_context *ctx = &brw->ctx;
if (srgb_decode == GL_SKIP_DECODE_EXT)
src/mesa/drivers/dri/i965/brw_urb.c
+35 -35
View File
@@ -89,11 +89,11 @@ static const struct {
GLuint min_entry_size;
GLuint max_entry_size;
} limits[CS+1] = {
{ 16, 32, 1, 5 }, /* vs */
{ 4, 8, 1, 5 }, /* gs */
{ 5, 10, 1, 5 }, /* clp */
{ 1, 8, 1, 12 }, /* sf */
{ 1, 4, 1, 32 } /* cs */
{ 16, 32, 1, 5 }, /* vs */
{ 4, 8, 1, 5 }, /* gs */
{ 5, 10, 1, 5 }, /* clp */
{ 1, 8, 1, 12 }, /* sf */
{ 1, 4, 1, 32 } /* cs */
};
@@ -131,8 +131,8 @@ brw_calculate_urb_fence(struct brw_context *brw, unsigned csize,
brw->urb.sfsize < sfsize ||
brw->urb.csize < csize ||
(brw->urb.constrained && (brw->urb.vsize > vsize ||
brw->urb.sfsize > sfsize ||
brw->urb.csize > csize))) {
brw->urb.sfsize > sfsize ||
brw->urb.csize > csize))) {
brw->urb.csize = csize;
@@ -158,44 +158,44 @@ brw_calculate_urb_fence(struct brw_context *brw, unsigned csize,
brw->urb.nr_sf_entries = limits[SF].preferred_nr_entries;
}
} else if (devinfo->is_g4x) {
brw->urb.nr_vs_entries = 64;
if (check_urb_layout(brw)) {
goto done;
} else {
brw->urb.constrained = 1;
brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries;
}
brw->urb.nr_vs_entries = 64;
if (check_urb_layout(brw)) {
goto done;
} else {
brw->urb.constrained = 1;
brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries;
}
}
if (!check_urb_layout(brw)) {
brw->urb.nr_vs_entries = limits[VS].min_nr_entries;
brw->urb.nr_gs_entries = limits[GS].min_nr_entries;
brw->urb.nr_clip_entries = limits[CLP].min_nr_entries;
brw->urb.nr_sf_entries = limits[SF].min_nr_entries;
brw->urb.nr_cs_entries = limits[CS].min_nr_entries;
brw->urb.nr_vs_entries = limits[VS].min_nr_entries;
brw->urb.nr_gs_entries = limits[GS].min_nr_entries;
brw->urb.nr_clip_entries = limits[CLP].min_nr_entries;
brw->urb.nr_sf_entries = limits[SF].min_nr_entries;
brw->urb.nr_cs_entries = limits[CS].min_nr_entries;
/* Mark us as operating with constrained nr_entries, so that next
* time we recalculate we'll resize the fences in the hope of
* escaping constrained mode and getting back to normal performance.
*/
brw->urb.constrained = 1;
/* Mark us as operating with constrained nr_entries, so that next
* time we recalculate we'll resize the fences in the hope of
* escaping constrained mode and getting back to normal performance.
*/
brw->urb.constrained = 1;
if (!check_urb_layout(brw)) {
/* This is impossible, given the maximal sizes of urb
* entries and the values for minimum nr of entries
* provided above.
*/
fprintf(stderr, "couldn't calculate URB layout!\n");
exit(1);
}
if (!check_urb_layout(brw)) {
/* This is impossible, given the maximal sizes of urb
* entries and the values for minimum nr of entries
* provided above.
*/
fprintf(stderr, "couldn't calculate URB layout!\n");
exit(1);
}
if (INTEL_DEBUG & (DEBUG_URB|DEBUG_PERF))
fprintf(stderr, "URB CONSTRAINED\n");
if (INTEL_DEBUG & (DEBUG_URB|DEBUG_PERF))
fprintf(stderr, "URB CONSTRAINED\n");
}
done:
if (INTEL_DEBUG & DEBUG_URB)
fprintf(stderr,
fprintf(stderr,
"URB fence: %d ..VS.. %d ..GS.. %d ..CLP.. %d ..SF.. %d ..CS.. %d\n",
brw->urb.vs_start,
brw->urb.gs_start,
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+26 -26
View File
@@ -701,7 +701,7 @@ brw_update_buffer_texture_surface(struct gl_context *ctx,
if (isl_format == ISL_FORMAT_UNSUPPORTED) {
_mesa_problem(NULL, "bad format %s for texture buffer\n",
_mesa_get_format_name(format));
_mesa_get_format_name(format));
}
brw_emit_buffer_surface_state(brw, surf_offset, bo,
@@ -785,7 +785,7 @@ brw_update_sol_surface(struct brw_context *brw,
surf[1] = brw_state_reloc(&brw->batch,
*out_offset + 4, bo, offset_bytes, RELOC_WRITE);
surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
height << BRW_SURFACE_HEIGHT_SHIFT);
height << BRW_SURFACE_HEIGHT_SHIFT);
surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
surf[4] = 0;
@@ -876,7 +876,7 @@ emit_null_surface_state(struct brw_context *brw,
size_needed);
surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
ISL_FORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
ISL_FORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
surf[1] = brw_state_reloc(&brw->batch, *out_offset + 4,
brw->wm.multisampled_null_render_target_bo,
0, RELOC_WRITE);
@@ -922,15 +922,15 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
brw_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y);
if (tile_x != 0 || tile_y != 0) {
/* Original gen4 hardware couldn't draw to a non-tile-aligned
* destination in a miptree unless you actually setup your renderbuffer
* as a miptree and used the fragile lod/array_index/etc. controls to
* select the image. So, instead, we just make a new single-level
* miptree and render into that.
*/
brw_renderbuffer_move_to_temp(brw, irb, false);
assert(irb->align_wa_mt);
mt = irb->align_wa_mt;
/* Original gen4 hardware couldn't draw to a non-tile-aligned
* destination in a miptree unless you actually setup your renderbuffer
* as a miptree and used the fragile lod/array_index/etc. controls to
* select the image. So, instead, we just make a new single-level
* miptree and render into that.
*/
brw_renderbuffer_move_to_temp(brw, irb, false);
assert(irb->align_wa_mt);
mt = irb->align_wa_mt;
}
}
@@ -943,7 +943,7 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
}
surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
format << BRW_SURFACE_FORMAT_SHIFT);
format << BRW_SURFACE_FORMAT_SHIFT);
/* reloc */
assert(mt->offset % mt->cpp == 0);
@@ -955,10 +955,10 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
RELOC_WRITE);
surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
(rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
(rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
surf[3] = (brw_get_surface_tiling_bits(mt->surf.tiling) |
(mt->surf.row_pitch_B - 1) << BRW_SURFACE_PITCH_SHIFT);
(mt->surf.row_pitch_B - 1) << BRW_SURFACE_PITCH_SHIFT);
surf[4] = brw_get_surface_num_multisamples(mt->surf.samples);
@@ -969,8 +969,8 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
assert(tile_x % 4 == 0);
assert(tile_y % 2 == 0);
surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
(tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
(mt->surf.image_alignment_el.height == 4 ?
(tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
(mt->surf.image_alignment_el.height == 4 ?
BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
if (devinfo->gen < 6) {
@@ -978,21 +978,21 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
if (!ctx->Color.ColorLogicOpEnabled &&
ctx->Color._AdvancedBlendMode == BLEND_NONE &&
(ctx->Color.BlendEnabled & (1 << unit)))
surf[0] |= BRW_SURFACE_BLEND_ENABLED;
surf[0] |= BRW_SURFACE_BLEND_ENABLED;
if (!GET_COLORMASK_BIT(ctx->Color.ColorMask, unit, 0))
surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
if (!GET_COLORMASK_BIT(ctx->Color.ColorMask, unit, 1))
surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
if (!GET_COLORMASK_BIT(ctx->Color.ColorMask, unit, 2))
surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
/* As mentioned above, disable writes to the alpha component when the
* renderbuffer is XRGB.
*/
if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
!GET_COLORMASK_BIT(ctx->Color.ColorMask, unit, 3)) {
surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
!GET_COLORMASK_BIT(ctx->Color.ColorMask, unit, 3)) {
surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
}
}
@@ -1018,13 +1018,13 @@ update_renderbuffer_surfaces(struct brw_context *brw)
for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) {
struct gl_renderbuffer *rb = fb->_ColorDrawBuffers[i];
if (brw_renderbuffer(rb)) {
if (brw_renderbuffer(rb)) {
surf_offsets[rt_start + i] = devinfo->gen >= 6 ?
gen6_update_renderbuffer_surface(brw, rb, i, rt_start + i) :
gen4_update_renderbuffer_surface(brw, rb, i, rt_start + i);
} else {
} else {
emit_null_surface_state(brw, fb, &surf_offsets[rt_start + i]);
}
}
}
} else {
emit_null_surface_state(brw, fb, &surf_offsets[rt_start]);
src/mesa/drivers/dri/i965/gen6_constant_state.c
+4 -4
View File
@@ -240,8 +240,8 @@ brw_upload_pull_constants(struct brw_context *brw,
if (!prog_data->nr_pull_params) {
if (stage_state->surf_offset[surf_index]) {
stage_state->surf_offset[surf_index] = 0;
brw->ctx.NewDriverState |= brw_new_constbuf;
stage_state->surf_offset[surf_index] = 0;
brw->ctx.NewDriverState |= brw_new_constbuf;
}
return;
}
@@ -266,8 +266,8 @@ brw_upload_pull_constants(struct brw_context *brw,
if (0) {
for (i = 0; i < ALIGN(prog_data->nr_pull_params, 4) / 4; i++) {
const gl_constant_value *row = &constants[i * 4];
fprintf(stderr, "const surface %3d: %4.3f %4.3f %4.3f %4.3f\n",
const gl_constant_value *row = &constants[i * 4];
fprintf(stderr, "const surface %3d: %4.3f %4.3f %4.3f %4.3f\n",
i, row[0].f, row[1].f, row[2].f, row[3].f);
}
}
src/mesa/drivers/dri/i965/gen6_sampler_state.c
+4 -4
View File
@@ -35,10 +35,10 @@ upload_sampler_state_pointers(struct brw_context *brw)
{
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS << 16 |
VS_SAMPLER_STATE_CHANGE |
GS_SAMPLER_STATE_CHANGE |
PS_SAMPLER_STATE_CHANGE |
(4 - 2));
VS_SAMPLER_STATE_CHANGE |
GS_SAMPLER_STATE_CHANGE |
PS_SAMPLER_STATE_CHANGE |
(4 - 2));
OUT_BATCH(brw->vs.base.sampler_offset); /* VS */
OUT_BATCH(brw->gs.base.sampler_offset); /* GS */
OUT_BATCH(brw->wm.base.sampler_offset);
src/mesa/drivers/dri/i965/gen6_sol.c
+1 -1
View File
@@ -386,7 +386,7 @@ brw_get_transform_feedback_vertex_count(struct gl_context *ctx,
void
brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
struct gl_transform_feedback_object *obj)
struct gl_transform_feedback_object *obj)
{
struct brw_context *brw = brw_context(ctx);
const struct gl_program *prog;
src/mesa/drivers/dri/i965/gen6_urb.c
+2 -2
View File
@@ -84,9 +84,9 @@ gen6_upload_urb(struct brw_context *brw, unsigned vs_size,
BEGIN_BATCH(3);
OUT_BATCH(_3DSTATE_URB << 16 | (3 - 2));
OUT_BATCH(((vs_size - 1) << GEN6_URB_VS_SIZE_SHIFT) |
((brw->urb.nr_vs_entries) << GEN6_URB_VS_ENTRIES_SHIFT));
((brw->urb.nr_vs_entries) << GEN6_URB_VS_ENTRIES_SHIFT));
OUT_BATCH(((gs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) |
((brw->urb.nr_gs_entries) << GEN6_URB_GS_ENTRIES_SHIFT));
((brw->urb.nr_gs_entries) << GEN6_URB_GS_ENTRIES_SHIFT));
ADVANCE_BATCH();
/* From the PRM Volume 2 part 1, section 1.4.7:
src/mesa/drivers/dri/i965/gen7_sol_state.c
+1 -1
View File
@@ -63,7 +63,7 @@ gen7_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
void
gen7_end_transform_feedback(struct gl_context *ctx,
struct gl_transform_feedback_object *obj)
struct gl_transform_feedback_object *obj)
{
/* After EndTransformFeedback, it's likely that the client program will try
* to draw using the contents of the transform feedback buffer as vertex
src/mesa/drivers/dri/i965/genX_state_upload.c
+6 -6
View File
@@ -5652,9 +5652,9 @@ genX(init_atoms)(struct brw_context *brw)
&genX(cc_vp),
&gen6_urb,
&genX(blend_state), /* must do before cc unit */
&genX(color_calc_state), /* must do before cc unit */
&genX(depth_stencil_state), /* must do before cc unit */
&genX(blend_state), /* must do before cc unit */
&genX(color_calc_state), /* must do before cc unit */
&genX(depth_stencil_state), /* must do before cc unit */
&genX(vs_push_constants), /* Before vs_state */
&genX(gs_push_constants), /* Before gs_state */
@@ -5722,10 +5722,10 @@ genX(init_atoms)(struct brw_context *brw)
#if GEN_IS_HASWELL
&genX(cc_and_blend_state),
#else
&genX(blend_state), /* must do before cc unit */
&genX(color_calc_state), /* must do before cc unit */
&genX(blend_state), /* must do before cc unit */
&genX(color_calc_state), /* must do before cc unit */
#endif
&genX(depth_stencil_state), /* must do before cc unit */
&genX(depth_stencil_state), /* must do before cc unit */
&brw_vs_image_surfaces, /* Before vs push/pull constants and binding table */
&brw_tcs_image_surfaces, /* Before tcs push/pull constants and binding table */
src/mesa/drivers/dri/i965/hsw_sol.c
+1 -1
View File
@@ -249,7 +249,7 @@ hsw_resume_transform_feedback(struct gl_context *ctx,
*/
void
hsw_end_transform_feedback(struct gl_context *ctx,
struct gl_transform_feedback_object *obj)
struct gl_transform_feedback_object *obj)
{
struct brw_context *brw = brw_context(ctx);
struct brw_transform_feedback_object *brw_obj =
src/mesa/drivers/dri/i965/intel_batchbuffer.h
+1 -1
View File
@@ -108,7 +108,7 @@ brw_batch_advance(struct brw_context *brw)
assert(batch->total != 0);
if (_n != batch->total) {
fprintf(stderr, "ADVANCE_BATCH: %d of %d dwords emitted\n",
_n, batch->total);
_n, batch->total);
abort();
}
batch->total = 0;
src/mesa/drivers/dri/i965/intel_blit.c
+2 -2
View File
@@ -634,9 +634,9 @@ brw_emit_immediate_color_expand_blit(struct brw_context *brw,
if (dst_tiling != ISL_TILING_LINEAR) {
if (dst_offset & 4095)
return false;
return false;
if (dst_tiling == ISL_TILING_Y0)
return false;
return false;
}
assert((unsigned) logic_op <= 0x0f);
src/mesa/drivers/dri/i965/intel_fbo.c
+43 -43
View File
@@ -269,10 +269,10 @@ brw_renderbuffer_format(struct gl_context * ctx, GLenum internalFormat)
case GL_STENCIL_INDEX16_EXT:
/* These aren't actual texture formats, so force them here. */
if (brw->has_separate_stencil) {
return MESA_FORMAT_S_UINT8;
return MESA_FORMAT_S_UINT8;
} else {
assert(!devinfo->must_use_separate_stencil);
return MESA_FORMAT_Z24_UNORM_S8_UINT;
assert(!devinfo->must_use_separate_stencil);
return MESA_FORMAT_Z24_UNORM_S8_UINT;
}
}
}
@@ -571,7 +571,7 @@ brw_renderbuffer_set_draw_offset(struct brw_renderbuffer *irb)
/* compute offset of the particular 2D image within the texture region */
brw_miptree_get_image_offset(irb->mt, irb->mt_level, irb->mt_layer,
&dst_x, &dst_y);
&dst_x, &dst_y);
irb->draw_x = dst_x;
irb->draw_y = dst_y;
@@ -657,14 +657,14 @@ brw_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb)
DBG("%s() on fb %p (%s)\n", __func__,
fb, (fb == ctx->DrawBuffer ? "drawbuffer" :
(fb == ctx->ReadBuffer ? "readbuffer" : "other buffer")));
(fb == ctx->ReadBuffer ? "readbuffer" : "other buffer")));
if (depthRb)
depth_mt = depthRb->mt;
if (stencilRb) {
stencil_mt = stencilRb->mt;
if (stencil_mt->stencil_mt)
stencil_mt = stencil_mt->stencil_mt;
stencil_mt = stencil_mt->stencil_mt;
}
if (depth_mt && stencil_mt) {
@@ -686,52 +686,52 @@ brw_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb)
* the depth & stencil attachments to match in various more retrictive
* ways. (width, height, depth, LOD and layer)
*/
if (d_width != s_width ||
if (d_width != s_width ||
d_height != s_height ||
d_depth != s_depth ||
depthRb->mt_level != stencilRb->mt_level ||
depthRb->mt_layer != stencilRb->mt_layer) {
fbo_incomplete(fb, GL_FRAMEBUFFER_UNSUPPORTED,
depthRb->mt_layer != stencilRb->mt_layer) {
fbo_incomplete(fb, GL_FRAMEBUFFER_UNSUPPORTED,
"FBO incomplete: depth and stencil must match in"
"width, height, depth, LOD and layer\n");
}
}
}
if (depth_mt == stencil_mt) {
/* For true packed depth/stencil (not faked on prefers-separate-stencil
* hardware) we need to be sure they're the same level/layer, since
* we'll be emitting a single packet describing the packed setup.
*/
if (depthRb->mt_level != stencilRb->mt_level ||
depthRb->mt_layer != stencilRb->mt_layer) {
fbo_incomplete(fb, GL_FRAMEBUFFER_UNSUPPORTED,
/* For true packed depth/stencil (not faked on prefers-separate-stencil
* hardware) we need to be sure they're the same level/layer, since
* we'll be emitting a single packet describing the packed setup.
*/
if (depthRb->mt_level != stencilRb->mt_level ||
depthRb->mt_layer != stencilRb->mt_layer) {
fbo_incomplete(fb, GL_FRAMEBUFFER_UNSUPPORTED,
"FBO incomplete: depth image level/layer %d/%d != "
"stencil image %d/%d\n",
depthRb->mt_level,
depthRb->mt_layer,
stencilRb->mt_level,
stencilRb->mt_layer);
}
}
} else {
if (!brw->has_separate_stencil) {
fbo_incomplete(fb, GL_FRAMEBUFFER_UNSUPPORTED,
if (!brw->has_separate_stencil) {
fbo_incomplete(fb, GL_FRAMEBUFFER_UNSUPPORTED,
"FBO incomplete: separate stencil unsupported\n");
}
if (stencil_mt->format != MESA_FORMAT_S_UINT8) {
fbo_incomplete(fb, GL_FRAMEBUFFER_UNSUPPORTED,
}
if (stencil_mt->format != MESA_FORMAT_S_UINT8) {
fbo_incomplete(fb, GL_FRAMEBUFFER_UNSUPPORTED,
"FBO incomplete: separate stencil is %s "
"instead of S8\n",
_mesa_get_format_name(stencil_mt->format));
}
if (devinfo->gen < 7 && !brw_renderbuffer_has_hiz(depthRb)) {
/* Before Gen7, separate depth and stencil buffers can be used
* only if HiZ is enabled. From the Sandybridge PRM, Volume 2,
* Part 1, Bit 3DSTATE_DEPTH_BUFFER.SeparateStencilBufferEnable:
* [DevSNB]: This field must be set to the same value (enabled
* or disabled) as Hierarchical Depth Buffer Enable.
*/
fbo_incomplete(fb, GL_FRAMEBUFFER_UNSUPPORTED,
}
if (devinfo->gen < 7 && !brw_renderbuffer_has_hiz(depthRb)) {
/* Before Gen7, separate depth and stencil buffers can be used
* only if HiZ is enabled. From the Sandybridge PRM, Volume 2,
* Part 1, Bit 3DSTATE_DEPTH_BUFFER.SeparateStencilBufferEnable:
* [DevSNB]: This field must be set to the same value (enabled
* or disabled) as Hierarchical Depth Buffer Enable.
*/
fbo_incomplete(fb, GL_FRAMEBUFFER_UNSUPPORTED,
"FBO incomplete: separate stencil without HiZ\n");
}
}
}
}
@@ -740,7 +740,7 @@ brw_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb)
struct brw_renderbuffer *irb;
if (fb->Attachment[i].Type == GL_NONE)
continue;
continue;
/* A supported attachment will have a Renderbuffer set either
* from being a Renderbuffer or being a texture that got the
@@ -748,25 +748,25 @@ brw_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb)
*/
rb = fb->Attachment[i].Renderbuffer;
if (rb == NULL) {
fbo_incomplete(fb, GL_FRAMEBUFFER_UNSUPPORTED,
fbo_incomplete(fb, GL_FRAMEBUFFER_UNSUPPORTED,
"FBO incomplete: attachment without "
"renderbuffer\n");
continue;
continue;
}
if (fb->Attachment[i].Type == GL_TEXTURE) {
if (rb->TexImage->Border) {
fbo_incomplete(fb, GL_FRAMEBUFFER_UNSUPPORTED,
if (rb->TexImage->Border) {
fbo_incomplete(fb, GL_FRAMEBUFFER_UNSUPPORTED,
"FBO incomplete: texture with border\n");
continue;
}
continue;
}
}
irb = brw_renderbuffer(rb);
if (irb == NULL) {
fbo_incomplete(fb, GL_FRAMEBUFFER_UNSUPPORTED,
fbo_incomplete(fb, GL_FRAMEBUFFER_UNSUPPORTED,
"FBO incomplete: software rendering renderbuffer\n");
continue;
continue;
}
if (rb->Format == MESA_FORMAT_R_SRGB8) {
@@ -777,7 +777,7 @@ brw_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb)
}
if (!brw_render_target_supported(brw, rb)) {
fbo_incomplete(fb, GL_FRAMEBUFFER_UNSUPPORTED,
fbo_incomplete(fb, GL_FRAMEBUFFER_UNSUPPORTED,
"FBO incomplete: Unsupported HW "
"texture/renderbuffer format attached: %s\n",
_mesa_get_format_name(brw_rb_format(irb)));
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+59 -59
View File
@@ -1030,7 +1030,7 @@ brw_miptree_release(struct brw_mipmap_tree **mt)
brw_miptree_release(&(*mt)->plane[1]);
for (i = 0; i < MAX_TEXTURE_LEVELS; i++) {
free((*mt)->level[i].slice);
free((*mt)->level[i].slice);
}
free(*mt);
@@ -2235,11 +2235,11 @@ brw_offset_S8(uint32_t stride, uint32_t x, uint32_t y, bool swizzled)
if (swizzled) {
/* adjust for bit6 swizzling */
if (((byte_x / 8) % 2) == 1) {
if (((byte_y / 8) % 2) == 0) {
u += 64;
} else {
u -= 64;
}
if (((byte_y / 8) % 2) == 0) {
u += 64;
} else {
u -= 64;
}
}
}
@@ -2753,13 +2753,13 @@ brw_miptree_unmap_s8(struct brw_context *brw,
brw_miptree_get_image_offset(mt, level, slice, &image_x, &image_y);
for (uint32_t y = 0; y < map->h; y++) {
for (uint32_t x = 0; x < map->w; x++) {
for (uint32_t x = 0; x < map->w; x++) {
ptrdiff_t offset = brw_offset_S8(mt->surf.row_pitch_B,
image_x + x + map->x,
image_y + y + map->y,
brw->has_swizzling);
tiled_s8_map[offset] = untiled_s8_map[y * map->w + x];
}
tiled_s8_map[offset] = untiled_s8_map[y * map->w + x];
}
}
brw_miptree_unmap_raw(mt);
@@ -2795,24 +2795,24 @@ brw_miptree_map_s8(struct brw_context *brw,
brw_miptree_get_image_offset(mt, level, slice, &image_x, &image_y);
for (uint32_t y = 0; y < map->h; y++) {
for (uint32_t x = 0; x < map->w; x++) {
for (uint32_t x = 0; x < map->w; x++) {
ptrdiff_t offset = brw_offset_S8(mt->surf.row_pitch_B,
x + image_x + map->x,
y + image_y + map->y,
brw->has_swizzling);
untiled_s8_map[y * map->w + x] = tiled_s8_map[offset];
}
untiled_s8_map[y * map->w + x] = tiled_s8_map[offset];
}
}
brw_miptree_unmap_raw(mt);
DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__,
map->x, map->y, map->w, map->h,
mt, map->x + image_x, map->y + image_y, map->ptr, map->stride);
map->x, map->y, map->w, map->h,
mt, map->x + image_x, map->y + image_y, map->ptr, map->stride);
} else {
DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__,
map->x, map->y, map->w, map->h,
mt, map->ptr, map->stride);
map->x, map->y, map->w, map->h,
mt, map->ptr, map->stride);
}
map->unmap = brw_miptree_unmap_s8;
@@ -2853,36 +2853,36 @@ brw_miptree_unmap_depthstencil(struct brw_context *brw,
&z_image_x, &z_image_y);
for (uint32_t y = 0; y < map->h; y++) {
for (uint32_t x = 0; x < map->w; x++) {
for (uint32_t x = 0; x < map->w; x++) {
ptrdiff_t s_offset = brw_offset_S8(s_mt->surf.row_pitch_B,
x + s_image_x + map->x,
y + s_image_y + map->y,
brw->has_swizzling);
ptrdiff_t z_offset = ((y + z_image_y + map->y) *
ptrdiff_t z_offset = ((y + z_image_y + map->y) *
(z_mt->surf.row_pitch_B / 4) +
(x + z_image_x + map->x));
(x + z_image_x + map->x));
if (map_z32f_x24s8) {
z_map[z_offset] = packed_map[(y * map->w + x) * 2 + 0];
s_map[s_offset] = packed_map[(y * map->w + x) * 2 + 1];
} else {
uint32_t packed = packed_map[y * map->w + x];
s_map[s_offset] = packed >> 24;
z_map[z_offset] = packed;
}
}
if (map_z32f_x24s8) {
z_map[z_offset] = packed_map[(y * map->w + x) * 2 + 0];
s_map[s_offset] = packed_map[(y * map->w + x) * 2 + 1];
} else {
uint32_t packed = packed_map[y * map->w + x];
s_map[s_offset] = packed >> 24;
z_map[z_offset] = packed;
}
}
}
brw_miptree_unmap_raw(s_mt);
brw_miptree_unmap_raw(z_mt);
DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
__func__,
map->x, map->y, map->w, map->h,
z_mt, _mesa_get_format_name(z_mt->format),
map->x + z_image_x, map->y + z_image_y,
s_mt, map->x + s_image_x, map->y + s_image_y,
map->ptr, map->stride);
__func__,
map->x, map->y, map->w, map->h,
z_mt, _mesa_get_format_name(z_mt->format),
map->x + z_image_x, map->y + z_image_y,
s_mt, map->x + s_image_x, map->y + s_image_y,
map->ptr, map->stride);
}
free(map->buffer);
@@ -2927,40 +2927,40 @@ brw_miptree_map_depthstencil(struct brw_context *brw,
&z_image_x, &z_image_y);
for (uint32_t y = 0; y < map->h; y++) {
for (uint32_t x = 0; x < map->w; x++) {
int map_x = map->x + x, map_y = map->y + y;
ptrdiff_t s_offset = brw_offset_S8(s_mt->surf.row_pitch_B,
map_x + s_image_x,
map_y + s_image_y,
brw->has_swizzling);
ptrdiff_t z_offset = ((map_y + z_image_y) *
for (uint32_t x = 0; x < map->w; x++) {
int map_x = map->x + x, map_y = map->y + y;
ptrdiff_t s_offset = brw_offset_S8(s_mt->surf.row_pitch_B,
map_x + s_image_x,
map_y + s_image_y,
brw->has_swizzling);
ptrdiff_t z_offset = ((map_y + z_image_y) *
(z_mt->surf.row_pitch_B / 4) +
(map_x + z_image_x));
uint8_t s = s_map[s_offset];
uint32_t z = z_map[z_offset];
(map_x + z_image_x));
uint8_t s = s_map[s_offset];
uint32_t z = z_map[z_offset];
if (map_z32f_x24s8) {
packed_map[(y * map->w + x) * 2 + 0] = z;
packed_map[(y * map->w + x) * 2 + 1] = s;
} else {
packed_map[y * map->w + x] = (s << 24) | (z & 0x00ffffff);
}
}
if (map_z32f_x24s8) {
packed_map[(y * map->w + x) * 2 + 0] = z;
packed_map[(y * map->w + x) * 2 + 1] = s;
} else {
packed_map[y * map->w + x] = (s << 24) | (z & 0x00ffffff);
}
}
}
brw_miptree_unmap_raw(s_mt);
brw_miptree_unmap_raw(z_mt);
DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
__func__,
map->x, map->y, map->w, map->h,
z_mt, map->x + z_image_x, map->y + z_image_y,
s_mt, map->x + s_image_x, map->y + s_image_y,
map->ptr, map->stride);
__func__,
map->x, map->y, map->w, map->h,
z_mt, map->x + z_image_x, map->y + z_image_y,
s_mt, map->x + s_image_x, map->y + s_image_y,
map->ptr, map->stride);
} else {
DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__,
map->x, map->y, map->w, map->h,
mt, map->ptr, map->stride);
map->x, map->y, map->w, map->h,
mt, map->ptr, map->stride);
}
map->unmap = brw_miptree_unmap_depthstencil;
@@ -3132,7 +3132,7 @@ brw_miptree_unmap(struct brw_context *brw,
mt, _mesa_get_format_name(mt->format), level, slice);
if (map->unmap)
map->unmap(brw, mt, map, level, slice);
map->unmap(brw, mt, map, level, slice);
brw_miptree_release_map(mt, level, slice);
}
src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+1 -1
View File
@@ -73,7 +73,7 @@ struct brw_texture_image;
* However, occasionally you want to actually map the miptree's current data
* without transcoding back. This flag to brw_miptree_map() gets you that.
*/
#define BRW_MAP_DIRECT_BIT 0x80000000
#define BRW_MAP_DIRECT_BIT 0x80000000
struct brw_miptree_map {
/** Bitfield of GL_MAP_*_BIT and BRW_MAP_*_BIT. */
src/mesa/drivers/dri/i965/intel_pixel.c
+7 -7
View File
@@ -41,9 +41,9 @@ effective_func(GLenum func, bool src_alpha_is_one)
{
if (src_alpha_is_one) {
if (func == GL_SRC_ALPHA)
return GL_ONE;
return GL_ONE;
if (func == GL_ONE_MINUS_SRC_ALPHA)
return GL_ZERO;
return GL_ZERO;
}
return func;
@@ -66,11 +66,11 @@ brw_check_blit_fragment_ops(struct gl_context * ctx, bool src_alpha_is_one)
if (ctx->Color.BlendEnabled &&
(effective_func(ctx->Color.Blend[0].SrcRGB, src_alpha_is_one) != GL_ONE ||
effective_func(ctx->Color.Blend[0].DstRGB, src_alpha_is_one) != GL_ZERO ||
ctx->Color.Blend[0].EquationRGB != GL_FUNC_ADD ||
effective_func(ctx->Color.Blend[0].SrcA, src_alpha_is_one) != GL_ONE ||
effective_func(ctx->Color.Blend[0].DstA, src_alpha_is_one) != GL_ZERO ||
ctx->Color.Blend[0].EquationA != GL_FUNC_ADD)) {
effective_func(ctx->Color.Blend[0].DstRGB, src_alpha_is_one) != GL_ZERO ||
ctx->Color.Blend[0].EquationRGB != GL_FUNC_ADD ||
effective_func(ctx->Color.Blend[0].SrcA, src_alpha_is_one) != GL_ONE ||
effective_func(ctx->Color.Blend[0].DstA, src_alpha_is_one) != GL_ZERO ||
ctx->Color.Blend[0].EquationA != GL_FUNC_ADD)) {
DBG("fallback due to blend\n");
return false;
}
src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
+63 -61
View File
@@ -59,23 +59,24 @@
* PBO bitmaps. I think they are probably pretty rare though - I
* wonder if Xgl uses them?
*/
static const GLubyte *map_pbo( struct gl_context *ctx,
GLsizei width, GLsizei height,
const struct gl_pixelstore_attrib *unpack,
const GLubyte *bitmap )
static const GLubyte *
map_pbo(struct gl_context *ctx,
GLsizei width, GLsizei height,
const struct gl_pixelstore_attrib *unpack,
const GLubyte *bitmap)
{
GLubyte *buf;
if (!_mesa_validate_pbo_access(2, unpack, width, height, 1,
GL_COLOR_INDEX, GL_BITMAP,
INT_MAX, (const GLvoid *) bitmap)) {
GL_COLOR_INDEX, GL_BITMAP,
INT_MAX, (const GLvoid *) bitmap)) {
_mesa_error(ctx, GL_INVALID_OPERATION,"glBitmap(invalid PBO access)");
return NULL;
}
buf = (GLubyte *) ctx->Driver.MapBufferRange(ctx, 0, unpack->BufferObj->Size,
GL_MAP_READ_BIT,
unpack->BufferObj,
GL_MAP_READ_BIT,
unpack->BufferObj,
MAP_INTERNAL);
if (!buf) {
_mesa_error(ctx, GL_INVALID_OPERATION, "glBitmap(PBO is mapped)");
@@ -98,14 +99,15 @@ static void set_bit( GLubyte *dest, GLuint bit )
/* Extract a rectangle's worth of data from the bitmap. Called
* per chunk of HW-sized bitmap.
*/
static GLuint get_bitmap_rect(GLsizei width, GLsizei height,
const struct gl_pixelstore_attrib *unpack,
const GLubyte *bitmap,
GLuint x, GLuint y,
GLuint w, GLuint h,
GLubyte *dest,
GLuint row_align,
bool invert)
static GLuint
get_bitmap_rect(GLsizei width, GLsizei height,
const struct gl_pixelstore_attrib *unpack,
const GLubyte *bitmap,
GLuint x, GLuint y,
GLuint w, GLuint h,
GLubyte *dest,
GLuint row_align,
bool invert)
{
GLuint src_offset = (x + unpack->SkipPixels) & 0x7;
GLuint mask = unpack->LsbFirst ? 0 : 7;
@@ -133,19 +135,19 @@ static GLuint get_bitmap_rect(GLsizei width, GLsizei height,
*/
for (row = first; row != (last+incr); row += incr) {
const GLubyte *rowsrc = _mesa_image_address2d(unpack, bitmap,
width, height,
GL_COLOR_INDEX, GL_BITMAP,
y + row, x);
width, height,
GL_COLOR_INDEX, GL_BITMAP,
y + row, x);
for (col = 0; col < w; col++, bit++) {
if (test_bit(rowsrc, (col + src_offset) ^ mask)) {
set_bit(dest, bit ^ 7);
count++;
}
if (test_bit(rowsrc, (col + src_offset) ^ mask)) {
set_bit(dest, bit ^ 7);
count++;
}
}
if (row_align)
bit = ALIGN(bit, row_align);
bit = ALIGN(bit, row_align);
}
return count;
@@ -168,11 +170,11 @@ y_flip(struct gl_framebuffer *fb, int y, int height)
* Render a bitmap.
*/
static bool
do_blit_bitmap( struct gl_context *ctx,
GLint dstx, GLint dsty,
GLsizei width, GLsizei height,
const struct gl_pixelstore_attrib *unpack,
const GLubyte *bitmap )
do_blit_bitmap(struct gl_context *ctx,
GLint dstx, GLint dsty,
GLsizei width, GLsizei height,
const struct gl_pixelstore_attrib *unpack,
const GLubyte *bitmap)
{
struct brw_context *brw = brw_context(ctx);
struct gl_framebuffer *fb = ctx->DrawBuffer;
@@ -211,7 +213,7 @@ do_blit_bitmap( struct gl_context *ctx,
if (unpack->BufferObj) {
bitmap = map_pbo(ctx, width, height, unpack, bitmap);
if (bitmap == NULL)
return true; /* even though this is an error, we're done */
return true; /* even though this is an error, we're done */
}
COPY_4V(tmpColor, ctx->Current.RasterColor);
@@ -244,8 +246,8 @@ do_blit_bitmap( struct gl_context *ctx,
/* Clip to buffer bounds and scissor. */
if (!_mesa_clip_to_region(fb->_Xmin, fb->_Ymin,
fb->_Xmax, fb->_Ymax,
&dstx, &dsty, &width, &height))
fb->_Xmax, fb->_Ymax,
&dstx, &dsty, &width, &height))
goto out;
dsty = y_flip(fb, dsty, height);
@@ -261,21 +263,21 @@ do_blit_bitmap( struct gl_context *ctx,
/* Chop it all into chunks that can be digested by hardware: */
for (py = 0; py < height; py += DY) {
for (px = 0; px < width; px += DX) {
int h = MIN2(DY, height - py);
int w = MIN2(DX, width - px);
GLuint sz = ALIGN(ALIGN(w,8) * h, 64)/8;
const enum gl_logicop_mode logic_op = ctx->Color.ColorLogicOpEnabled ?
ctx->Color._LogicOp : COLOR_LOGICOP_COPY;
int h = MIN2(DY, height - py);
int w = MIN2(DX, width - px);
GLuint sz = ALIGN(ALIGN(w,8) * h, 64)/8;
const enum gl_logicop_mode logic_op = ctx->Color.ColorLogicOpEnabled ?
ctx->Color._LogicOp : COLOR_LOGICOP_COPY;
assert(sz <= sizeof(stipple));
memset(stipple, 0, sz);
assert(sz <= sizeof(stipple));
memset(stipple, 0, sz);
/* May need to adjust this when padding has been introduced in
* sz above:
*
* Have to translate destination coordinates back into source
* coordinates.
*/
/* May need to adjust this when padding has been introduced in
* sz above:
*
* Have to translate destination coordinates back into source
* coordinates.
*/
int count = get_bitmap_rect(bitmap_width, bitmap_height, unpack,
bitmap,
-orig_dstx + (dstx + px),
@@ -285,23 +287,23 @@ do_blit_bitmap( struct gl_context *ctx,
8,
fb->FlipY);
if (count == 0)
continue;
continue;
if (!brw_emit_immediate_color_expand_blit(brw,
irb->mt->cpp,
(GLubyte *)stipple,
sz,
color,
irb->mt->surf.row_pitch_B,
irb->mt->bo,
irb->mt->offset,
irb->mt->surf.tiling,
dstx + px,
dsty + py,
w, h,
logic_op)) {
return false;
}
if (!brw_emit_immediate_color_expand_blit(brw,
irb->mt->cpp,
(GLubyte *)stipple,
sz,
color,
irb->mt->surf.row_pitch_B,
irb->mt->bo,
irb->mt->offset,
irb->mt->surf.tiling,
dstx + px,
dsty + py,
w, h,
logic_op)) {
return false;
}
if (ctx->Query.CurrentOcclusionObject)
ctx->Query.CurrentOcclusionObject->Result += count;
src/mesa/drivers/dri/i965/intel_pixel_copy.c
+7 -7
View File
@@ -68,8 +68,8 @@ do_blit_copypixels(struct gl_context * ctx,
switch (type) {
case GL_COLOR:
if (fb->_NumColorDrawBuffers != 1) {
perf_debug("glCopyPixels() fallback: MRT\n");
return false;
perf_debug("glCopyPixels() fallback: MRT\n");
return false;
}
draw_irb = brw_renderbuffer(fb->_ColorDrawBuffers[0]);
@@ -78,7 +78,7 @@ do_blit_copypixels(struct gl_context * ctx,
case GL_DEPTH_STENCIL_EXT:
draw_irb = brw_renderbuffer(fb->Attachment[BUFFER_DEPTH].Renderbuffer);
read_irb =
brw_renderbuffer(read_fb->Attachment[BUFFER_DEPTH].Renderbuffer);
brw_renderbuffer(read_fb->Attachment[BUFFER_DEPTH].Renderbuffer);
break;
case GL_DEPTH:
perf_debug("glCopyPixels() fallback: GL_DEPTH\n");
@@ -150,8 +150,8 @@ do_blit_copypixels(struct gl_context * ctx,
orig_dstx = dstx;
orig_dsty = dsty;
if (!_mesa_clip_to_region(fb->_Xmin, fb->_Ymin,
fb->_Xmax, fb->_Ymax,
&dstx, &dsty, &width, &height))
fb->_Xmax, fb->_Ymax,
&dstx, &dsty, &width, &height))
goto out;
/* Adjust src coords for our post-clipped destination origin */
srcx += dstx - orig_dstx;
@@ -161,8 +161,8 @@ do_blit_copypixels(struct gl_context * ctx,
orig_srcx = srcx;
orig_srcy = srcy;
if (!_mesa_clip_to_region(0, 0,
read_fb->Width, read_fb->Height,
&srcx, &srcy, &width, &height))
read_fb->Width, read_fb->Height,
&srcx, &srcy, &width, &height))
goto out;
/* Adjust dst coords for our post-clipped source origin */
dstx += srcx - orig_srcx;
src/mesa/drivers/dri/i965/intel_pixel_draw.c
+7 -7
View File
@@ -49,10 +49,10 @@
static bool
do_blit_drawpixels(struct gl_context * ctx,
GLint x, GLint y, GLsizei width, GLsizei height,
GLenum format, GLenum type,
const struct gl_pixelstore_attrib *unpack,
const GLvoid * pixels)
GLint x, GLint y, GLsizei width, GLsizei height,
GLenum format, GLenum type,
const struct gl_pixelstore_attrib *unpack,
const GLvoid * pixels)
{
struct brw_context *brw = brw_context(ctx);
struct brw_buffer_object *src = brw_buffer_object(unpack->BufferObj);
@@ -106,7 +106,7 @@ do_blit_drawpixels(struct gl_context * ctx,
src_offset = (GLintptr)pixels;
src_offset += _mesa_image_offset(2, unpack, width, height,
format, type, 0, 0, 0);
format, type, 0, 0, 0);
src_buffer = brw_bufferobj_buffer(brw, src, src_offset,
height * src_stride, false);
@@ -166,8 +166,8 @@ brw_drawpixels(struct gl_context *ctx,
if (brw->screen->devinfo.gen < 6 &&
unpack->BufferObj) {
if (do_blit_drawpixels(ctx, x, y, width, height, format, type, unpack,
pixels)) {
return;
pixels)) {
return;
}
perf_debug("%s: fallback to generic code in PBO case\n", __func__);
src/mesa/drivers/dri/i965/intel_screen.c
+11 -11
View File
@@ -463,7 +463,7 @@ brw_allocate_image(struct brw_screen *screen, int dri_format,
image = calloc(1, sizeof *image);
if (image == NULL)
return NULL;
return NULL;
image->screen = screen;
image->dri_format = dri_format;
@@ -737,7 +737,7 @@ brw_create_image_common(__DRIscreen *dri_screen,
if (use & __DRI_IMAGE_USE_CURSOR) {
if (width != 64 || height != 64)
return NULL;
return NULL;
modifier = DRM_FORMAT_MOD_LINEAR;
}
@@ -1038,7 +1038,7 @@ brw_validate_usage(__DRIimage *image, unsigned int use)
{
if (use & __DRI_IMAGE_USE_CURSOR) {
if (image->width != 64 || image->height != 64)
return GL_FALSE;
return GL_FALSE;
}
return GL_TRUE;
@@ -1584,14 +1584,14 @@ brw_query_renderer_integer(__DRIscreen *dri_screen,
case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY:
value[0] = 0;
if (brw_hw_context_set_priority(screen->bufmgr,
0, GEN_CONTEXT_HIGH_PRIORITY) == 0)
0, GEN_CONTEXT_HIGH_PRIORITY) == 0)
value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH;
if (brw_hw_context_set_priority(screen->bufmgr,
0, GEN_CONTEXT_LOW_PRIORITY) == 0)
0, GEN_CONTEXT_LOW_PRIORITY) == 0)
value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW;
/* reset to default last, just in case */
if (brw_hw_context_set_priority(screen->bufmgr,
0, GEN_CONTEXT_MEDIUM_PRIORITY) == 0)
0, GEN_CONTEXT_MEDIUM_PRIORITY) == 0)
value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM;
return 0;
case __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB:
@@ -1948,7 +1948,7 @@ brw_init_bufmgr(struct brw_screen *screen)
screen->bufmgr = brw_bufmgr_get_for_fd(&screen->devinfo, dri_screen->fd, bo_reuse);
if (screen->bufmgr == NULL) {
fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n",
__func__, __LINE__);
__func__, __LINE__);
return false;
}
screen->fd = brw_bufmgr_get_fd(screen->bufmgr);
@@ -2570,8 +2570,8 @@ __DRIconfig **brw_init_screen(__DRIscreen *dri_screen)
} else if (dri_screen->dri2.loader->base.version <= 2 ||
dri_screen->dri2.loader->getBuffersWithFormat == NULL) {
fprintf(stderr,
"\nERROR! DRI2 loader with getBuffersWithFormat() "
"support required\n");
"\nERROR! DRI2 loader with getBuffersWithFormat() "
"support required\n");
return NULL;
}
@@ -2920,8 +2920,8 @@ brw_allocate_buffer(__DRIscreen *dri_screen,
BO_ALLOC_BUSY);
if (buffer->bo == NULL) {
free(buffer);
return NULL;
free(buffer);
return NULL;
}
brw_bo_flink(buffer->bo, &buffer->base.name);
src/mesa/drivers/dri/i965/intel_tex.c
+1 -2
View File
@@ -221,8 +221,7 @@ brw_map_texture_image(struct gl_context *ctx,
assert(mt);
/* Check that our caller wasn't confused about how to map a 1D texture. */
assert(tex_image->TexObject->Target != GL_TEXTURE_1D_ARRAY ||
h == 1);
assert(tex_image->TexObject->Target != GL_TEXTURE_1D_ARRAY || h == 1);
/* brw_miptree_map operates on a unified "slice" number that references the
* cube face, since it's all just slices to the miptree code.
src/mesa/drivers/dri/i965/intel_tex_image.c
+4 -5
View File
@@ -432,8 +432,8 @@ brw_set_texture_image_mt(struct brw_context *brw,
void
brw_set_texbuffer2(__DRIcontext *pDRICtx, GLint target,
GLint texture_format,
__DRIdrawable *dPriv)
GLint texture_format,
__DRIdrawable *dPriv)
{
struct gl_framebuffer *fb = dPriv->driverPrivate;
struct brw_context *brw = pDRICtx->driverPrivate;
@@ -577,9 +577,8 @@ brw_bind_renderbuffer_tex_image(struct gl_context *ctx,
return false;
_mesa_lock_texture(ctx, texobj);
_mesa_init_teximage_fields(ctx, image,
rb->Width, rb->Height, 1,
0, rb->InternalFormat, rb->Format);
_mesa_init_teximage_fields(ctx, image, rb->Width, rb->Height, 1, 0,
rb->InternalFormat, rb->Format);
image->NumSamples = rb->NumSamples;
brw_miptree_reference(&intel_image->mt, irb->mt);
src/mesa/drivers/dri/i965/intel_tex_validate.c
+5 -5
View File
@@ -110,8 +110,8 @@ brw_finalize_mipmap_tree(struct brw_context *brw,
*/
if (brw_obj->mt &&
(!brw_miptree_match_image(brw_obj->mt, &firstImage->base.Base) ||
validate_first_level < brw_obj->mt->first_level ||
validate_last_level > brw_obj->mt->last_level)) {
validate_first_level < brw_obj->mt->first_level ||
validate_last_level > brw_obj->mt->last_level)) {
brw_miptree_release(&brw_obj->mt);
}
@@ -171,9 +171,9 @@ brw_finalize_mipmap_tree(struct brw_context *brw,
for (i = validate_first_level; i <= validate_last_level; i++) {
struct brw_texture_image *brw_image =
brw_texture_image(brw_obj->base.Image[face][i]);
/* skip too small size mipmap */
if (brw_image == NULL)
break;
/* skip too small size mipmap */
if (brw_image == NULL)
break;
if (brw_obj->mt != brw_image->mt)
brw_miptree_copy_teximage(brw, brw_image, brw_obj->mt);