brw: enable vertex fetching component packing
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32418>
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Lionel Landwerlin
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Marge Bot
Marge Bot
parent
9b8d75c95c
commit
4f892ae4f7
@@ -28,6 +28,159 @@ brw_assign_vs_urb_setup(brw_shader &s)
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}
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}
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static unsigned
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brw_nir_pack_vs_input(nir_shader *nir, struct brw_vs_prog_data *prog_data)
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{
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struct vf_attribute {
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unsigned reg_offset;
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uint8_t component_mask;
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bool is_64bit:1;
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bool is_used:1;
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} attributes[MAX_HW_VERT_ATTRIB] = {};
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/* IO lowering is going to break dmat inputs into a location each, so we
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* need to reproduce the 64bit nature of the variable into each slot.
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*/
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nir_foreach_shader_in_variable(var, nir) {
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const bool is_64bit = glsl_type_is_64bit(var->type);
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const uint32_t slots = glsl_count_vec4_slots(var->type, true, false);
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for (uint32_t i = 0; i < slots; i++)
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attributes[var->data.location + i].is_64bit = is_64bit;
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}
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/* First mark all used inputs */
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nir_foreach_function_impl(impl, nir) {
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nir_foreach_block(block, impl) {
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nir_foreach_instr(instr, block) {
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if (instr->type != nir_instr_type_intrinsic)
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continue;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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if (intrin->intrinsic != nir_intrinsic_load_input)
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continue;
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assert(intrin->def.bit_size == 32);
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const struct nir_io_semantics io =
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nir_intrinsic_io_semantics(intrin);
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attributes[io.location].is_used = true;
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/* SKL PRMs, Vol 2a: Command Reference: Instructions,
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* 3DSTATE_VF_COMPONENT_PACKING:
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*
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* "Software shall enable all components (XYZW) for any and all
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* VERTEX_ELEMENTs associated with a 256-bit SURFACE_FORMAT.
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* It is INVALID to disable any components in these cases."
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*
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* Enable this XYZW for any > 128-bit format.
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*/
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if (nir->info.dual_slot_inputs & BITFIELD64_BIT(io.location)) {
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attributes[io.location].component_mask |= 0xff;
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} else {
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const uint8_t mask =
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nir_component_mask(intrin->num_components) <<
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nir_intrinsic_component(intrin);
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attributes[io.location].component_mask |= mask;
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}
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}
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}
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}
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/* Compute the register offsets */
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unsigned reg_offset = 0;
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unsigned vertex_element = 0;
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for (unsigned a = 0; a < ARRAY_SIZE(attributes); a++) {
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if (!attributes[a].is_used)
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continue;
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/* SKL PRMs, Vol 2a: Command Reference: Instructions,
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* 3DSTATE_VF_COMPONENT_PACKING:
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*
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* "No enable bits are provided for Vertex Elements [32-33],
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* and therefore no packing is performed on these elements (if
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* Valid, all 4 components are stored)."
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*/
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if (vertex_element >= 32)
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attributes[a].component_mask = 0xf;
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attributes[a].reg_offset = reg_offset;
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reg_offset += util_bitcount(attributes[a].component_mask);
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vertex_element++;
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}
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/* Remap inputs */
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nir_foreach_function_impl(impl, nir) {
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nir_foreach_block(block, impl) {
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nir_foreach_instr(instr, block) {
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if (instr->type != nir_instr_type_intrinsic)
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continue;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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if (intrin->intrinsic != nir_intrinsic_load_input)
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continue;
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struct nir_io_semantics io = nir_intrinsic_io_semantics(intrin);
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unsigned slot = attributes[io.location].reg_offset / 4;
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unsigned slot_component =
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attributes[io.location].reg_offset % 4 +
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util_bitcount(attributes[io.location].component_mask &
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BITFIELD_MASK(io.high_dvec2 * 4 +
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nir_intrinsic_component(intrin)));
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slot += slot_component / 4;
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slot_component %= 4;
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nir_intrinsic_set_base(intrin, slot);
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nir_intrinsic_set_component(intrin, slot_component);
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}
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}
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}
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/* Generate the packing array */
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unsigned vf_offset = 0;
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for (unsigned a = 0; a < ARRAY_SIZE(attributes) && vf_offset < 32; a++) {
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if (!attributes[a].is_used)
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continue;
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uint32_t mask;
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/* Stores masks in attributes[a].component_mask are in terms of 32-bit
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* components, but the HW depending on the format will interpret
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* prog_data->vf_component_packing[] bits as either a 32-bit or 64-bit
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* component. So we need to only consider every other bit.
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*/
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if (attributes[a].is_64bit) {
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mask = 0;
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u_foreach_bit(b, attributes[a].component_mask)
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mask |= BITFIELD_BIT(b / 2);
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} else {
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mask = attributes[a].component_mask;
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}
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/* We should only have 4bits enabled max */
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assert((mask & ~0xfu) == 0);
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prog_data->vf_component_packing[vf_offset / 8] |=
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mask << (4 * (vf_offset % 8));
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vf_offset++;
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}
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/* SKL PRMs, Vol 2a: Command Reference: Instructions,
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* 3DSTATE_VF_COMPONENT_PACKING:
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*
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* "At least one component of one "valid" Vertex Element must be
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* enabled."
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*/
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if (prog_data->vf_component_packing[0] == 0 &&
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prog_data->vf_component_packing[1] == 0 &&
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prog_data->vf_component_packing[2] == 0 &&
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prog_data->vf_component_packing[3] == 0)
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prog_data->vf_component_packing[0] = 0x1;
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return reg_offset;
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}
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static bool
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run_vs(brw_shader &s)
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{
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@@ -83,6 +236,13 @@ brw_compile_vs(const struct brw_compiler *compiler,
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brw_nir_lower_vs_inputs(nir);
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brw_nir_lower_vue_outputs(nir);
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memset(prog_data->vf_component_packing, 0,
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sizeof(prog_data->vf_component_packing));
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unsigned nr_packed_regs = 0;
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if (key->vf_component_packing)
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nr_packed_regs = brw_nir_pack_vs_input(nir, prog_data);
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brw_postprocess_nir(nir, compiler, debug_enabled,
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key->base.robust_flags);
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@@ -127,8 +287,14 @@ brw_compile_vs(const struct brw_compiler *compiler,
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if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID))
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prog_data->uses_drawid = true;
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prog_data->base.urb_read_length = DIV_ROUND_UP(nr_attribute_slots, 2);
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unsigned nr_attribute_regs = 4 * nr_attribute_slots;
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unsigned nr_attribute_regs;
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if (key->vf_component_packing) {
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prog_data->base.urb_read_length = DIV_ROUND_UP(nr_packed_regs, 8);
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nr_attribute_regs = nr_packed_regs;
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} else {
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prog_data->base.urb_read_length = DIV_ROUND_UP(nr_attribute_slots, 2);
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nr_attribute_regs = 4 * (nr_attribute_slots);
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}
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/* Since vertex shaders reuse the same VUE entry for inputs and outputs
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* (overwriting the original contents), we need to make sure the size is
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@@ -233,6 +233,16 @@ struct brw_base_prog_key {
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/** The program key for Vertex Shaders. */
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struct brw_vs_prog_key {
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struct brw_base_prog_key base;
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/** Enable component packing
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*
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* Using this option requires that the driver programs
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* 3DSTATE_VF_COMPONENT_PACKING with the values provided in
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* brw_vs_prog_data::vf_component_packing
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*/
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bool vf_component_packing : 1;
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uint32_t padding : 31;
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};
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/** The program key for Tessellation Control Shaders. */
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@@ -1028,6 +1038,8 @@ struct brw_vs_prog_data {
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bool uses_firstvertex;
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bool uses_baseinstance;
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bool uses_drawid;
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uint32_t vf_component_packing[4];
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};
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struct brw_tcs_prog_data
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