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i965: switch tes over to shared shader_info

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Note we access shader_info from the program struct rather than the
nir_shader pointer because shader cache won't create a nir_shader.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Timothy Arceri
2016-10-19 10:19:27 +11:00
parent 088c25bfb7
commit 4f1c415cc4
2 changed files with 8 additions and 8 deletions
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src/mesa/drivers/dri/i965/brw_tcs.c
+3 -3
View File
@@ -341,10 +341,10 @@ brw_tcs_populate_key(struct brw_context *brw,
/* We need to specialize our code generation for tessellation levels
* based on the domain the DS is expecting to tessellate.
*/
key->tes_primitive_mode = tep->program.PrimitiveMode;
key->tes_primitive_mode = tep->program.Base.info.tes.primitive_mode;
key->quads_workaround = brw->gen < 9 &&
tep->program.PrimitiveMode == GL_QUADS &&
tep->program.Spacing == GL_EQUAL;
tep->program.Base.info.tes.primitive_mode == GL_QUADS &&
tep->program.Base.info.tes.spacing == GL_EQUAL;
if (tcp) {
key->program_string_id = tcp->id;
src/mesa/drivers/dri/i965/brw_tes.c
+5 -5
View File
@@ -96,7 +96,7 @@ brw_codegen_tes_prog(struct brw_context *brw,
shader_prog, &tep->program.Base,
&prog_data.base.base, 0);
switch (tep->program.Spacing) {
switch (tep->program.Base.info.tes.spacing) {
case GL_EQUAL:
prog_data.partitioning = BRW_TESS_PARTITIONING_INTEGER;
break;
@@ -110,7 +110,7 @@ brw_codegen_tes_prog(struct brw_context *brw,
unreachable("invalid domain shader spacing");
}
switch (tep->program.PrimitiveMode) {
switch (tep->program.Base.info.tes.primitive_mode) {
case GL_QUADS:
prog_data.domain = BRW_TESS_DOMAIN_QUAD;
break;
@@ -124,13 +124,13 @@ brw_codegen_tes_prog(struct brw_context *brw,
unreachable("invalid domain shader primitive mode");
}
if (tep->program.PointMode) {
if (tep->program.Base.info.tes.point_mode) {
prog_data.output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
} else if (tep->program.PrimitiveMode == GL_ISOLINES) {
} else if (tep->program.Base.info.tes.primitive_mode == GL_ISOLINES) {
prog_data.output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
} else {
/* Hardware winding order is backwards from OpenGL */
switch (tep->program.VertexOrder) {
switch (tep->program.Base.info.tes.vertex_order) {
case GL_CCW:
prog_data.output_topology = BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW;
break;