r300/compiler: Implement branch emulation for R300 fragment programs
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
This commit is contained in:
Nicolai Hähnle
committed by
Marek Olšák
Marek Olšák
parent
eeabe9d179
commit
4d7ed84431
@@ -8,6 +8,7 @@ LIBNAME = r300compiler
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C_SOURCES = \
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radeon_code.c \
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radeon_compiler.c \
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radeon_emulate_branches.c \
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radeon_program.c \
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radeon_program_print.c \
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radeon_opcodes.c \
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@@ -46,4 +46,35 @@ void memory_pool_init(struct memory_pool * pool);
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void memory_pool_destroy(struct memory_pool * pool);
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void * memory_pool_malloc(struct memory_pool * pool, unsigned int bytes);
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/**
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* Generic helper for growing an array that has separate size/count
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* and reserved counters to accomodate up to num new element.
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*
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* type * Array;
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* unsigned int Size;
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* unsigned int Reserved;
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*
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* memory_pool_array_reserve(pool, type, Array, Size, Reserved, k);
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* assert(Size + k < Reserved);
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*
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* \note Size is not changed by this macro.
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*
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* \warning Array, Size, Reserved have to be lvalues and may be evaluated
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* several times.
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*/
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#define memory_pool_array_reserve(pool, type, array, size, reserved, num) do { \
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unsigned int _num = (num); \
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if ((size) + _num > (reserved)) { \
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unsigned int newreserve = (reserved) * 2; \
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type * newarray; \
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if (newreserve < _num) \
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newreserve = 4 * _num; /* arbitrary heuristic */ \
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newarray = memory_pool_malloc((pool), newreserve * sizeof(type)); \
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memcpy(newarray, (array), (size) * sizeof(type)); \
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(array) = newarray; \
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(reserved) = newreserve; \
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} \
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} while(0)
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#endif /* MEMORY_POOL_H */
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@@ -25,6 +25,7 @@
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#include <stdio.h>
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#include "radeon_dataflow.h"
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#include "radeon_emulate_branches.h"
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#include "radeon_program_alu.h"
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#include "radeon_program_tex.h"
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#include "r300_fragprog.h"
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@@ -85,6 +86,14 @@ static void rewrite_depth_out(struct r300_fragment_program_compiler * c)
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}
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}
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static void debug_program_log(struct r300_fragment_program_compiler* c, const char * where)
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{
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if (c->Base.Debug) {
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fprintf(stderr, "Fragment Program: %s\n", where);
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rc_print_program(&c->Base.Program);
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}
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}
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void r3xx_compile_fragment_program(struct r300_fragment_program_compiler* c)
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{
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rewrite_depth_out(c);
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@@ -106,6 +115,10 @@ void r3xx_compile_fragment_program(struct r300_fragment_program_compiler* c)
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};
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radeonLocalTransform(&c->Base, 2, transformations);
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debug_program_log(c, "before emulate branches");
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rc_emulate_branches(&c->Base);
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c->Base.SwizzleCaps = &r300_swizzle_caps;
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}
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@@ -119,62 +132,41 @@ void r3xx_compile_fragment_program(struct r300_fragment_program_compiler* c)
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common_transformations[0].function = &radeonTransformALU;
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radeonLocalTransform(&c->Base, 1, common_transformations);
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if (c->Base.Debug) {
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fprintf(stderr, "Fragment Program: After native rewrite:\n");
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rc_print_program(&c->Base.Program);
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fflush(stderr);
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}
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if (c->Base.Error)
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return;
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debug_program_log(c, "after native rewrite");
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rc_dataflow_deadcode(&c->Base, &dataflow_outputs_mark_use, c);
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if (c->Base.Error)
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return;
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if (c->Base.Debug) {
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fprintf(stderr, "Fragment Program: After deadcode:\n");
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rc_print_program(&c->Base.Program);
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fflush(stderr);
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}
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debug_program_log(c, "after deadcode");
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rc_dataflow_swizzles(&c->Base);
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if (c->Base.Error)
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return;
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if (c->Base.Debug) {
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fprintf(stderr, "Compiler: after dataflow passes:\n");
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rc_print_program(&c->Base.Program);
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fflush(stderr);
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}
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debug_program_log(c, "after dataflow passes");
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rc_pair_translate(c);
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if (c->Base.Error)
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return;
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if (c->Base.Debug) {
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fprintf(stderr, "Compiler: after pair translate:\n");
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rc_print_program(&c->Base.Program);
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fflush(stderr);
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}
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debug_program_log(c, "after pair translate");
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rc_pair_schedule(c);
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if (c->Base.Error)
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return;
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if (c->Base.Debug) {
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fprintf(stderr, "Compiler: after pair scheduling:\n");
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rc_print_program(&c->Base.Program);
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fflush(stderr);
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}
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debug_program_log(c, "after pair scheduling");
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rc_pair_regalloc(c, c->max_temp_regs);
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if (c->Base.Error)
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return;
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if (c->Base.Debug) {
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fprintf(stderr, "Compiler: after pair register allocation:\n");
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rc_print_program(&c->Base.Program);
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fflush(stderr);
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}
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debug_program_log(c, "after register allocation");
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if (c->is_r500) {
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r500BuildFragmentProgramHwCode(c);
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@@ -160,3 +160,92 @@ void rc_for_all_writes(struct rc_instruction * inst, rc_read_write_fn cb, void *
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writes_pair(inst, cb, userdata);
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}
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}
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static void remap_normal_instruction(struct rc_instruction * fullinst,
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rc_remap_register_fn cb, void * userdata)
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{
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struct rc_sub_instruction * inst = &fullinst->U.I;
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const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->Opcode);
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if (opcode->HasDstReg) {
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rc_register_file file = inst->DstReg.File;
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unsigned int index = inst->DstReg.Index;
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cb(userdata, fullinst, &file, &index);
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inst->DstReg.File = file;
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inst->DstReg.Index = index;
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}
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for(unsigned int src = 0; src < opcode->NumSrcRegs; ++src) {
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rc_register_file file = inst->SrcReg[src].File;
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unsigned int index = inst->SrcReg[src].Index;
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cb(userdata, fullinst, &file, &index);
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inst->SrcReg[src].File = file;
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inst->SrcReg[src].Index = index;
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}
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}
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static void remap_pair_instruction(struct rc_instruction * fullinst,
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rc_remap_register_fn cb, void * userdata)
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{
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struct rc_pair_instruction * inst = &fullinst->U.P;
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if (inst->RGB.WriteMask) {
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rc_register_file file = RC_FILE_TEMPORARY;
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unsigned int index = inst->RGB.DestIndex;
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cb(userdata, fullinst, &file, &index);
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inst->RGB.DestIndex = index;
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}
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if (inst->Alpha.WriteMask) {
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rc_register_file file = RC_FILE_TEMPORARY;
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unsigned int index = inst->Alpha.DestIndex;
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cb(userdata, fullinst, &file, &index);
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inst->Alpha.DestIndex = index;
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}
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for(unsigned int src = 0; src < 3; ++src) {
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if (inst->RGB.Src[src].Used) {
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rc_register_file file = inst->RGB.Src[src].File;
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unsigned int index = inst->RGB.Src[src].Index;
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cb(userdata, fullinst, &file, &index);
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inst->RGB.Src[src].File = file;
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inst->RGB.Src[src].Index = index;
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}
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if (inst->Alpha.Src[src].Used) {
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rc_register_file file = inst->Alpha.Src[src].File;
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unsigned int index = inst->Alpha.Src[src].Index;
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cb(userdata, fullinst, &file, &index);
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inst->Alpha.Src[src].File = file;
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inst->Alpha.Src[src].Index = index;
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}
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}
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}
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/**
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* Remap all register accesses according to the given function.
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* That is, call the function \p cb for each referenced register (both read and written)
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* and update the given instruction \p inst accordingly
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* if it modifies its \ref pfile and \ref pindex contents.
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*/
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void rc_remap_registers(struct rc_instruction * inst, rc_remap_register_fn cb, void * userdata)
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{
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if (inst->Type == RC_INSTRUCTION_NORMAL)
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remap_normal_instruction(inst, cb, userdata);
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else
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remap_pair_instruction(inst, cb, userdata);
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}
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@@ -36,13 +36,17 @@ struct rc_swizzle_caps;
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/**
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* Help analyze the register accesses of instructions.
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* Help analyze and modify the register accesses of instructions.
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*/
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/*@{*/
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typedef void (*rc_read_write_fn)(void * userdata, struct rc_instruction * inst,
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rc_register_file file, unsigned int index, unsigned int chan);
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void rc_for_all_reads(struct rc_instruction * inst, rc_read_write_fn cb, void * userdata);
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void rc_for_all_writes(struct rc_instruction * inst, rc_read_write_fn cb, void * userdata);
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typedef void (*rc_remap_register_fn)(void * userdata, struct rc_instruction * inst,
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rc_register_file * pfile, unsigned int * pindex);
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void rc_remap_registers(struct rc_instruction * inst, rc_remap_register_fn cb, void * userdata);
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/*@}*/
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@@ -0,0 +1,331 @@
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/*
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* Copyright 2009 Nicolai Hähnle <nhaehnle@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE. */
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#include "radeon_emulate_branches.h"
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#include <stdio.h>
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#include "radeon_compiler.h"
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#include "radeon_dataflow.h"
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#define VERBOSE 0
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#define DBG(...) do { if (VERBOSE) fprintf(stderr, __VA_ARGS__); } while(0)
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struct proxy_info {
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unsigned int Proxied:1;
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unsigned int Index:RC_REGISTER_INDEX_BITS;
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};
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struct register_proxies {
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struct proxy_info Temporary[RC_REGISTER_MAX_INDEX];
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};
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struct branch_info {
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struct rc_instruction * If;
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struct rc_instruction * Else;
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};
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struct emulate_branch_state {
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struct radeon_compiler * C;
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struct branch_info * Branches;
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unsigned int BranchCount;
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unsigned int BranchReserved;
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};
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static void handle_if(struct emulate_branch_state * s, struct rc_instruction * inst)
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{
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memory_pool_array_reserve(&s->C->Pool, struct branch_info,
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s->Branches, s->BranchCount, s->BranchReserved, 1);
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DBG("%s\n", __FUNCTION__);
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struct branch_info * branch = &s->Branches[s->BranchCount++];
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memset(branch, 0, sizeof(struct branch_info));
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branch->If = inst;
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/* Make a safety copy of the decision register, because we will need
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* it at ENDIF time and it might be overwritten in both branches. */
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struct rc_instruction * inst_mov = rc_insert_new_instruction(s->C, inst->Prev);
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inst_mov->U.I.Opcode = RC_OPCODE_MOV;
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inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY;
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inst_mov->U.I.DstReg.Index = rc_find_free_temporary(s->C);
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inst_mov->U.I.DstReg.WriteMask = RC_MASK_X;
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inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
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inst->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
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inst->U.I.SrcReg[0].Index = inst_mov->U.I.DstReg.Index;
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inst->U.I.SrcReg[0].Swizzle = 0;
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inst->U.I.SrcReg[0].Abs = 0;
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inst->U.I.SrcReg[0].Negate = 0;
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}
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static void handle_else(struct emulate_branch_state * s, struct rc_instruction * inst)
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{
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if (!s->BranchCount) {
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rc_error(s->C, "Encountered ELSE outside of branches");
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return;
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}
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DBG("%s\n", __FUNCTION__);
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struct branch_info * branch = &s->Branches[s->BranchCount - 1];
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branch->Else = inst;
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}
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struct state_and_proxies {
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struct emulate_branch_state * S;
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struct register_proxies * Proxies;
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};
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static struct proxy_info * get_proxy_info(struct state_and_proxies * sap,
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rc_register_file file, unsigned int index)
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{
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if (file == RC_FILE_TEMPORARY) {
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return &sap->Proxies->Temporary[index];
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} else {
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return 0;
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}
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}
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static void scan_write(void * userdata, struct rc_instruction * inst,
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rc_register_file file, unsigned int index, unsigned int comp)
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{
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struct state_and_proxies * sap = userdata;
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struct proxy_info * proxy = get_proxy_info(sap, file, index);
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if (proxy && !proxy->Proxied) {
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proxy->Proxied = 1;
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proxy->Index = rc_find_free_temporary(sap->S->C);
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}
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}
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static void remap_proxy_function(void * userdata, struct rc_instruction * inst,
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rc_register_file * pfile, unsigned int * pindex)
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{
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struct state_and_proxies * sap = userdata;
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struct proxy_info * proxy = get_proxy_info(sap, *pfile, *pindex);
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if (proxy && proxy->Proxied) {
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*pfile = RC_FILE_TEMPORARY;
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*pindex = proxy->Index;
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}
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}
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/**
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* Redirect all writes in the instruction range [begin, end) to proxy
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* temporary registers.
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*/
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static void allocate_and_insert_proxies(struct emulate_branch_state * s,
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struct register_proxies * proxies,
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struct rc_instruction * begin,
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struct rc_instruction * end)
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{
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struct state_and_proxies sap;
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sap.S = s;
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sap.Proxies = proxies;
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for(struct rc_instruction * inst = begin; inst != end; inst = inst->Next) {
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rc_for_all_writes(inst, scan_write, &sap);
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rc_remap_registers(inst, remap_proxy_function, &sap);
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}
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for(unsigned int index = 0; index < RC_REGISTER_MAX_INDEX; ++index) {
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if (proxies->Temporary[index].Proxied) {
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struct rc_instruction * inst_mov = rc_insert_new_instruction(s->C, begin->Prev);
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inst_mov->U.I.Opcode = RC_OPCODE_MOV;
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inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY;
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inst_mov->U.I.DstReg.Index = proxies->Temporary[index].Index;
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inst_mov->U.I.DstReg.WriteMask = RC_MASK_XYZW;
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inst_mov->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
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inst_mov->U.I.SrcReg[0].Index = index;
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}
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}
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}
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static void inject_cmp(struct emulate_branch_state * s,
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struct rc_instruction * inst_if,
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struct rc_instruction * inst_endif,
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rc_register_file file, unsigned int index,
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struct proxy_info ifproxy,
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struct proxy_info elseproxy)
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{
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struct rc_instruction * inst_cmp = rc_insert_new_instruction(s->C, inst_endif);
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inst_cmp->U.I.Opcode = RC_OPCODE_CMP;
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inst_cmp->U.I.DstReg.File = file;
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inst_cmp->U.I.DstReg.Index = index;
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inst_cmp->U.I.DstReg.WriteMask = RC_MASK_XYZW;
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inst_cmp->U.I.SrcReg[0] = inst_if->U.I.SrcReg[0];
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inst_cmp->U.I.SrcReg[0].Abs = 1;
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inst_cmp->U.I.SrcReg[0].Negate = RC_MASK_XYZW;
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inst_cmp->U.I.SrcReg[1].File = RC_FILE_TEMPORARY;
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inst_cmp->U.I.SrcReg[1].Index = ifproxy.Proxied ? ifproxy.Index : index;
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inst_cmp->U.I.SrcReg[2].File = RC_FILE_TEMPORARY;
|
||||
inst_cmp->U.I.SrcReg[2].Index = elseproxy.Proxied ? elseproxy.Index : index;
|
||||
}
|
||||
|
||||
static void handle_endif(struct emulate_branch_state * s, struct rc_instruction * inst)
|
||||
{
|
||||
if (!s->BranchCount) {
|
||||
rc_error(s->C, "Encountered ENDIF outside of branches");
|
||||
return;
|
||||
}
|
||||
|
||||
DBG("%s\n", __FUNCTION__);
|
||||
|
||||
struct branch_info * branch = &s->Branches[s->BranchCount - 1];
|
||||
struct register_proxies IfProxies;
|
||||
struct register_proxies ElseProxies;
|
||||
|
||||
memset(&IfProxies, 0, sizeof(IfProxies));
|
||||
memset(&ElseProxies, 0, sizeof(ElseProxies));
|
||||
|
||||
allocate_and_insert_proxies(s, &IfProxies, branch->If->Next, branch->Else ? branch->Else : inst);
|
||||
|
||||
if (branch->Else)
|
||||
allocate_and_insert_proxies(s, &ElseProxies, branch->Else->Next, inst);
|
||||
|
||||
/* Insert the CMP instructions at the end. */
|
||||
for(unsigned int index = 0; index < RC_REGISTER_MAX_INDEX; ++index) {
|
||||
if (IfProxies.Temporary[index].Proxied || ElseProxies.Temporary[index].Proxied) {
|
||||
inject_cmp(s, branch->If, inst, RC_FILE_TEMPORARY, index,
|
||||
IfProxies.Temporary[index], ElseProxies.Temporary[index]);
|
||||
}
|
||||
}
|
||||
|
||||
/* Remove all traces of the branch instructions */
|
||||
rc_remove_instruction(branch->If);
|
||||
if (branch->Else)
|
||||
rc_remove_instruction(branch->Else);
|
||||
rc_remove_instruction(inst);
|
||||
|
||||
s->BranchCount--;
|
||||
|
||||
if (VERBOSE) {
|
||||
DBG("Program after ENDIF handling:\n");
|
||||
rc_print_program(&s->C->Program);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
struct remap_output_data {
|
||||
unsigned int Output:RC_REGISTER_INDEX_BITS;
|
||||
unsigned int Temporary:RC_REGISTER_INDEX_BITS;
|
||||
};
|
||||
|
||||
static void remap_output_function(void * userdata, struct rc_instruction * inst,
|
||||
rc_register_file * pfile, unsigned int * pindex)
|
||||
{
|
||||
struct remap_output_data * data = userdata;
|
||||
|
||||
if (*pfile == RC_FILE_OUTPUT && *pindex == data->Output) {
|
||||
*pfile = RC_FILE_TEMPORARY;
|
||||
*pindex = data->Temporary;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Output registers cannot be read from and so cannot be dealt with like
|
||||
* temporary registers.
|
||||
*
|
||||
* We do the simplest thing: If an output registers is written within
|
||||
* a branch, then *all* writes to this register are proxied to a
|
||||
* temporary register, and a final MOV is appended to the end of
|
||||
* the program.
|
||||
*/
|
||||
static void fix_output_writes(struct emulate_branch_state * s, struct rc_instruction * inst)
|
||||
{
|
||||
if (!s->BranchCount)
|
||||
return;
|
||||
|
||||
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
|
||||
|
||||
if (!opcode->HasDstReg)
|
||||
return;
|
||||
|
||||
if (inst->U.I.DstReg.File == RC_FILE_OUTPUT) {
|
||||
struct remap_output_data remap;
|
||||
|
||||
remap.Output = inst->U.I.DstReg.Index;
|
||||
remap.Temporary = rc_find_free_temporary(s->C);
|
||||
|
||||
for(struct rc_instruction * inst = s->C->Program.Instructions.Next;
|
||||
inst != &s->C->Program.Instructions;
|
||||
inst = inst->Next) {
|
||||
rc_remap_registers(inst, &remap_output_function, &remap);
|
||||
}
|
||||
|
||||
struct rc_instruction * inst_mov = rc_insert_new_instruction(s->C, s->C->Program.Instructions.Prev);
|
||||
inst_mov->U.I.Opcode = RC_OPCODE_MOV;
|
||||
inst_mov->U.I.DstReg.File = RC_FILE_OUTPUT;
|
||||
inst_mov->U.I.DstReg.Index = remap.Output;
|
||||
inst_mov->U.I.DstReg.WriteMask = RC_MASK_XYZW;
|
||||
inst_mov->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
|
||||
inst_mov->U.I.SrcReg[0].Index = remap.Temporary;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Remove branch instructions; instead, execute both branches
|
||||
* on different register sets and choose between their results
|
||||
* using CMP instructions in place of the original ENDIF.
|
||||
*/
|
||||
void rc_emulate_branches(struct radeon_compiler * c)
|
||||
{
|
||||
struct emulate_branch_state s;
|
||||
|
||||
memset(&s, 0, sizeof(s));
|
||||
s.C = c;
|
||||
|
||||
/* Untypical loop because we may remove the current instruction */
|
||||
struct rc_instruction * ptr = c->Program.Instructions.Next;
|
||||
while(ptr != &c->Program.Instructions) {
|
||||
struct rc_instruction * inst = ptr;
|
||||
ptr = ptr->Next;
|
||||
|
||||
if (inst->Type == RC_INSTRUCTION_NORMAL) {
|
||||
switch(inst->U.I.Opcode) {
|
||||
case RC_OPCODE_IF:
|
||||
handle_if(&s, inst);
|
||||
break;
|
||||
case RC_OPCODE_ELSE:
|
||||
handle_else(&s, inst);
|
||||
break;
|
||||
case RC_OPCODE_ENDIF:
|
||||
handle_endif(&s, inst);
|
||||
break;
|
||||
default:
|
||||
fix_output_writes(&s, inst);
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
rc_error(c, "%s: unhandled instruction type\n", __FUNCTION__);
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* Copyright 2009 Nicolai Hähnle <nhaehnle@gmail.com>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* on the rights to use, copy, modify, merge, publish, distribute, sub
|
||||
* license, and/or sell copies of the Software, and to permit persons to whom
|
||||
* the Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
|
||||
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
|
||||
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||||
* USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef RADEON_EMULATE_BRANCHES_H
|
||||
#define RADEON_EMULATE_BRANCHES_H
|
||||
|
||||
struct radeon_compiler;
|
||||
|
||||
void rc_emulate_branches(struct radeon_compiler * c);
|
||||
|
||||
#endif /* RADEON_EMULATE_BRANCHES_H */
|
||||
@@ -196,9 +196,10 @@ static void compute_live_intervals(struct regalloc_state * s)
|
||||
}
|
||||
}
|
||||
|
||||
static void rewrite_register(struct regalloc_state * s,
|
||||
static void remap_register(void * data, struct rc_instruction * inst,
|
||||
rc_register_file * file, unsigned int * index)
|
||||
{
|
||||
struct regalloc_state * s = data;
|
||||
const struct register_info * reg;
|
||||
|
||||
if (*file == RC_FILE_TEMPORARY)
|
||||
@@ -214,74 +215,6 @@ static void rewrite_register(struct regalloc_state * s,
|
||||
}
|
||||
}
|
||||
|
||||
static void rewrite_normal_instruction(struct regalloc_state * s, struct rc_sub_instruction * inst)
|
||||
{
|
||||
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->Opcode);
|
||||
|
||||
if (opcode->HasDstReg) {
|
||||
rc_register_file file = inst->DstReg.File;
|
||||
unsigned int index = inst->DstReg.Index;
|
||||
|
||||
rewrite_register(s, &file, &index);
|
||||
|
||||
inst->DstReg.File = file;
|
||||
inst->DstReg.Index = index;
|
||||
}
|
||||
|
||||
for(unsigned int src = 0; src < opcode->NumSrcRegs; ++src) {
|
||||
rc_register_file file = inst->SrcReg[src].File;
|
||||
unsigned int index = inst->SrcReg[src].Index;
|
||||
|
||||
rewrite_register(s, &file, &index);
|
||||
|
||||
inst->SrcReg[src].File = file;
|
||||
inst->SrcReg[src].Index = index;
|
||||
}
|
||||
}
|
||||
|
||||
static void rewrite_pair_instruction(struct regalloc_state * s, struct rc_pair_instruction * inst)
|
||||
{
|
||||
if (inst->RGB.WriteMask) {
|
||||
rc_register_file file = RC_FILE_TEMPORARY;
|
||||
unsigned int index = inst->RGB.DestIndex;
|
||||
|
||||
rewrite_register(s, &file, &index);
|
||||
|
||||
inst->RGB.DestIndex = index;
|
||||
}
|
||||
|
||||
if (inst->Alpha.WriteMask) {
|
||||
rc_register_file file = RC_FILE_TEMPORARY;
|
||||
unsigned int index = inst->Alpha.DestIndex;
|
||||
|
||||
rewrite_register(s, &file, &index);
|
||||
|
||||
inst->Alpha.DestIndex = index;
|
||||
}
|
||||
|
||||
for(unsigned int src = 0; src < 3; ++src) {
|
||||
if (inst->RGB.Src[src].Used) {
|
||||
rc_register_file file = inst->RGB.Src[src].File;
|
||||
unsigned int index = inst->RGB.Src[src].Index;
|
||||
|
||||
rewrite_register(s, &file, &index);
|
||||
|
||||
inst->RGB.Src[src].File = file;
|
||||
inst->RGB.Src[src].Index = index;
|
||||
}
|
||||
|
||||
if (inst->Alpha.Src[src].Used) {
|
||||
rc_register_file file = inst->Alpha.Src[src].File;
|
||||
unsigned int index = inst->Alpha.Src[src].Index;
|
||||
|
||||
rewrite_register(s, &file, &index);
|
||||
|
||||
inst->Alpha.Src[src].File = file;
|
||||
inst->Alpha.Src[src].Index = index;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void do_regalloc(struct regalloc_state * s)
|
||||
{
|
||||
/* Simple and stupid greedy register allocation */
|
||||
@@ -310,10 +243,7 @@ static void do_regalloc(struct regalloc_state * s)
|
||||
for(struct rc_instruction * inst = s->C->Program.Instructions.Next;
|
||||
inst != &s->C->Program.Instructions;
|
||||
inst = inst->Next) {
|
||||
if (inst->Type == RC_INSTRUCTION_NORMAL)
|
||||
rewrite_normal_instruction(s, &inst->U.I);
|
||||
else
|
||||
rewrite_pair_instruction(s, &inst->U.P);
|
||||
rc_remap_registers(inst, &remap_register, s);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user