radv: delete winsys/null/*
The null device works without winsys, and now can be found in amd/common/ac_null_device.c. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37525>
This commit is contained in:
Daniel Schürmann
committed by
Marge Bot
Marge Bot
parent
7d6de8b17e
commit
4d68056e83
@@ -89,12 +89,6 @@ libradv_files = files(
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'nir/radv_nir_remap_color_attachment.c',
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'nir/radv_nir_rt_common.c',
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'nir/radv_nir_rt_shader.c',
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'winsys/null/radv_null_bo.c',
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'winsys/null/radv_null_bo.h',
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'winsys/null/radv_null_cs.c',
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'winsys/null/radv_null_cs.h',
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'winsys/null/radv_null_winsys.c',
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'winsys/null/radv_null_winsys_public.h',
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'radv_acceleration_structure.c',
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'radv_android.c',
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'radv_android.h',
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@@ -59,7 +59,6 @@ typedef void *drmDevicePtr;
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#include "util/u_atomic.h"
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#include "util/u_process.h"
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#include "vulkan/vk_icd.h"
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#include "winsys/null/radv_null_winsys_public.h"
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#include "git_sha1.h"
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#include "sid.h"
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#include "vk_format.h"
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@@ -1,73 +0,0 @@
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/*
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* Copyright © 2020 Valve Corporation
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*
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* based on amdgpu winsys.
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* SPDX-License-Identifier: MIT
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*/
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#include "radv_null_bo.h"
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#include "util/u_memory.h"
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static VkResult
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radv_null_winsys_bo_create(struct radeon_winsys *_ws, uint64_t size, unsigned alignment,
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enum radeon_bo_domain initial_domain, enum radeon_bo_flag flags, unsigned priority,
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uint64_t address, struct radeon_winsys_bo **out_bo)
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{
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struct radv_null_winsys_bo *bo;
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/* Courtesy for users using NULL to check if they need to destroy the BO. */
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*out_bo = NULL;
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bo = CALLOC_STRUCT(radv_null_winsys_bo);
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if (!bo)
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return VK_ERROR_OUT_OF_HOST_MEMORY;
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bo->ptr = malloc(size);
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if (!bo->ptr)
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goto error_ptr_alloc;
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*out_bo = (struct radeon_winsys_bo *)bo;
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return VK_SUCCESS;
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error_ptr_alloc:
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FREE(bo);
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return VK_ERROR_OUT_OF_HOST_MEMORY;
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}
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static void *
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radv_null_winsys_bo_map(struct radeon_winsys *_ws, struct radeon_winsys_bo *_bo, bool use_fixed_addr, void *fixed_addr)
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{
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struct radv_null_winsys_bo *bo = radv_null_winsys_bo(_bo);
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return bo->ptr;
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}
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static void
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radv_null_winsys_bo_unmap(struct radeon_winsys *_ws, struct radeon_winsys_bo *_bo, bool replace)
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{
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}
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static VkResult
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radv_null_winsys_bo_make_resident(struct radeon_winsys *_ws, struct radeon_winsys_bo *_bo, bool resident)
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{
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return VK_SUCCESS;
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}
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static void
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radv_null_winsys_bo_destroy(struct radeon_winsys *_ws, struct radeon_winsys_bo *_bo)
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{
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struct radv_null_winsys_bo *bo = radv_null_winsys_bo(_bo);
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FREE(bo->ptr);
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FREE(bo);
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}
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void
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radv_null_bo_init_functions(struct radv_null_winsys *ws)
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{
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ws->base.buffer_create = radv_null_winsys_bo_create;
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ws->base.buffer_destroy = radv_null_winsys_bo_destroy;
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ws->base.buffer_map = radv_null_winsys_bo_map;
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ws->base.buffer_unmap = radv_null_winsys_bo_unmap;
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ws->base.buffer_make_resident = radv_null_winsys_bo_make_resident;
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}
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@@ -1,30 +0,0 @@
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/*
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* Copyright © 2020 Valve Corporation
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*
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* based on amdgpu winsys.
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef RADV_NULL_BO_H
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#define RADV_NULL_BO_H
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#include "radv_null_winsys.h"
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struct radv_null_winsys_bo {
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struct radeon_winsys_bo base;
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struct radv_null_winsys *ws;
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void *ptr;
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};
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static inline struct radv_null_winsys_bo *
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radv_null_winsys_bo(struct radeon_winsys_bo *bo)
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{
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return (struct radv_null_winsys_bo *)bo;
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}
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void radv_null_bo_init_functions(struct radv_null_winsys *ws);
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#endif /* RADV_NULL_BO_H */
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@@ -1,98 +0,0 @@
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/*
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* Copyright © 2020 Valve Corporation
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*
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* based on amdgpu winsys.
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* SPDX-License-Identifier: MIT
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*/
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#include "radv_null_cs.h"
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#include "util/u_memory.h"
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struct radv_null_cs {
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struct ac_cmdbuf base;
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struct radv_null_winsys *ws;
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};
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static inline struct radv_null_cs *
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radv_null_cs(struct ac_cmdbuf *base)
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{
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return (struct radv_null_cs *)base;
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}
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static VkResult
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radv_null_ctx_create(struct radeon_winsys *_ws, enum radeon_ctx_priority priority, struct radeon_winsys_ctx **rctx)
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{
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struct radv_null_ctx *ctx = CALLOC_STRUCT(radv_null_ctx);
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if (!ctx)
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return VK_ERROR_OUT_OF_HOST_MEMORY;
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*rctx = (struct radeon_winsys_ctx *)ctx;
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return VK_SUCCESS;
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}
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static void
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radv_null_ctx_destroy(struct radeon_winsys_ctx *rwctx)
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{
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struct radv_null_ctx *ctx = (struct radv_null_ctx *)rwctx;
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FREE(ctx);
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}
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static enum radeon_bo_domain
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radv_null_cs_domain(const struct radeon_winsys *_ws)
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{
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return RADEON_DOMAIN_GTT;
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}
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static struct ac_cmdbuf *
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radv_null_cs_create(struct radeon_winsys *ws, enum amd_ip_type ip_type, UNUSED bool is_secondary)
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{
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struct radv_null_cs *cs = calloc(1, sizeof(struct radv_null_cs));
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if (!cs)
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return NULL;
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cs->ws = radv_null_winsys(ws);
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cs->base.buf = malloc(16384);
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cs->base.max_dw = 4096;
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if (!cs->base.buf) {
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FREE(cs);
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return NULL;
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}
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return &cs->base;
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}
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static void
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radv_null_cs_pad(struct ac_cmdbuf *_cs, unsigned leave_dw_space)
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{
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}
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static VkResult
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radv_null_cs_finalize(struct ac_cmdbuf *_cs)
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{
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return VK_SUCCESS;
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}
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static void
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radv_null_cs_destroy(struct ac_cmdbuf *_cs)
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{
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struct radv_null_cs *cs = radv_null_cs(_cs);
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FREE(cs->base.buf);
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FREE(cs);
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}
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void
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radv_null_cs_init_functions(struct radv_null_winsys *ws)
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{
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ws->base.ctx_create = radv_null_ctx_create;
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ws->base.ctx_destroy = radv_null_ctx_destroy;
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ws->base.cs_domain = radv_null_cs_domain;
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ws->base.cs_create = radv_null_cs_create;
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ws->base.cs_finalize = radv_null_cs_finalize;
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ws->base.cs_destroy = radv_null_cs_destroy;
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ws->base.cs_pad = radv_null_cs_pad;
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}
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@@ -1,29 +0,0 @@
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/*
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* Copyright © 2020 Valve Corporation
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*
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* based on amdgpu winsys.
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef RADV_NULL_CS_H
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#define RADV_NULL_CS_H
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#include "radv_null_winsys.h"
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#include "radv_radeon_winsys.h"
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struct radv_null_ctx {
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struct radv_null_winsys *ws;
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};
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static inline struct radv_null_ctx *
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radv_null_ctx(struct radeon_winsys_ctx *base)
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{
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return (struct radv_null_ctx *)base;
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}
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void radv_null_cs_init_functions(struct radv_null_winsys *ws);
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#endif /* RADV_NULL_CS_H */
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@@ -1,215 +0,0 @@
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/*
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* Copyright © 2020 Valve Corporation
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*
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* based on amdgpu winsys.
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* SPDX-License-Identifier: MIT
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*/
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#include "radv_null_winsys_public.h"
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#include "util/u_string.h"
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#include "util/u_sync_provider.h"
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#include "radv_null_bo.h"
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#include "radv_null_cs.h"
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#include "vk_sync_dummy.h"
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/* Hardcode some GPU info that are needed for the driver or for some tools. */
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static const struct {
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uint32_t pci_id;
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uint32_t num_render_backends;
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bool has_dedicated_vram;
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} pci_ids[] = {
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/* clang-format off */
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[CHIP_TAHITI] = {0x6780, 8, true},
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[CHIP_PITCAIRN] = {0x6800, 8, true},
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[CHIP_VERDE] = {0x6820, 4, true},
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[CHIP_OLAND] = {0x6060, 2, true},
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[CHIP_HAINAN] = {0x6660, 2, true},
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[CHIP_BONAIRE] = {0x6640, 4, true},
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[CHIP_KAVERI] = {0x1304, 2, false},
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[CHIP_KABINI] = {0x9830, 2, false},
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[CHIP_HAWAII] = {0x67A0, 16, true},
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[CHIP_TONGA] = {0x6920, 8, true},
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[CHIP_ICELAND] = {0x6900, 2, true},
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[CHIP_CARRIZO] = {0x9870, 2, false},
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[CHIP_FIJI] = {0x7300, 16, true},
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[CHIP_STONEY] = {0x98E4, 2, false},
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[CHIP_POLARIS10] = {0x67C0, 8, true},
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[CHIP_POLARIS11] = {0x67E0, 4, true},
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[CHIP_POLARIS12] = {0x6980, 4, true},
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[CHIP_VEGAM] = {0x694C, 4, true},
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[CHIP_VEGA10] = {0x6860, 16, true},
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[CHIP_VEGA12] = {0x69A0, 8, true},
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[CHIP_VEGA20] = {0x66A0, 16, true},
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[CHIP_RAVEN] = {0x15DD, 2, false},
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[CHIP_RENOIR] = {0x1636, 2, false},
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[CHIP_MI100] = {0x738C, 2, true},
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[CHIP_NAVI10] = {0x7310, 16, true},
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[CHIP_NAVI12] = {0x7360, 8, true},
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[CHIP_NAVI14] = {0x7340, 8, true},
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[CHIP_NAVI21] = {0x73A0, 16, true},
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[CHIP_VANGOGH] = {0x163F, 8, false},
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[CHIP_NAVI22] = {0x73C0, 8, true},
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[CHIP_NAVI23] = {0x73E0, 8, true},
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[CHIP_NAVI31] = {0x744C, 24, true},
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[CHIP_GFX1201] = {0x7550, 16, true},
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/* clang-format on */
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};
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static void
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radv_null_winsys_query_info(struct radeon_winsys *rws, struct radeon_info *gpu_info)
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{
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const char *family = os_get_option("RADV_FORCE_FAMILY");
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unsigned i;
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gpu_info->gfx_level = CLASS_UNKNOWN;
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gpu_info->family = CHIP_UNKNOWN;
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for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
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if (!strcasecmp(family, ac_get_family_name(i))) {
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/* Override family and gfx_level. */
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gpu_info->family = i;
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gpu_info->name = ac_get_family_name(i);
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if (gpu_info->family >= CHIP_GFX1200)
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gpu_info->gfx_level = GFX12;
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else if (gpu_info->family >= CHIP_NAVI31)
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gpu_info->gfx_level = GFX11;
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else if (i >= CHIP_NAVI21)
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gpu_info->gfx_level = GFX10_3;
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else if (i >= CHIP_NAVI10)
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gpu_info->gfx_level = GFX10;
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else if (i >= CHIP_VEGA10)
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gpu_info->gfx_level = GFX9;
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else if (i >= CHIP_TONGA)
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gpu_info->gfx_level = GFX8;
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else if (i >= CHIP_BONAIRE)
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gpu_info->gfx_level = GFX7;
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else
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gpu_info->gfx_level = GFX6;
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}
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}
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if (gpu_info->family == CHIP_UNKNOWN) {
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fprintf(stderr, "radv: Unknown family: %s\n", family);
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abort();
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}
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gpu_info->pci_id = pci_ids[gpu_info->family].pci_id;
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gpu_info->max_se = pci_ids[gpu_info->family].has_dedicated_vram ? 4 : 1;
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gpu_info->num_se = gpu_info->max_se;
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if (gpu_info->gfx_level >= GFX10_3)
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gpu_info->max_waves_per_simd = 16;
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else if (gpu_info->gfx_level >= GFX10)
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gpu_info->max_waves_per_simd = 20;
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else if (gpu_info->family >= CHIP_POLARIS10 && gpu_info->family <= CHIP_VEGAM)
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gpu_info->max_waves_per_simd = 8;
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else
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gpu_info->max_waves_per_simd = 10;
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if (gpu_info->gfx_level >= GFX10)
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gpu_info->num_physical_sgprs_per_simd = 128 * gpu_info->max_waves_per_simd;
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else if (gpu_info->gfx_level >= GFX8)
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gpu_info->num_physical_sgprs_per_simd = 800;
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else
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gpu_info->num_physical_sgprs_per_simd = 512;
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gpu_info->has_timeline_syncobj = true;
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gpu_info->has_vm_always_valid = true;
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gpu_info->has_3d_cube_border_color_mipmap = true;
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gpu_info->has_image_opcodes = true;
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gpu_info->has_attr_ring = gpu_info->gfx_level >= GFX11;
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gpu_info->has_attr_ring_wait_bug = gpu_info->gfx_level == GFX11 || gpu_info->gfx_level == GFX11_5;
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gpu_info->has_ngg_fully_culled_bug = gpu_info->gfx_level == GFX10;
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gpu_info->has_ngg_passthru_no_msg = gpu_info->family >= CHIP_NAVI23;
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if (gpu_info->family == CHIP_NAVI31 || gpu_info->family == CHIP_NAVI32 || gpu_info->gfx_level >= GFX12)
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gpu_info->num_physical_wave64_vgprs_per_simd = 768;
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else if (gpu_info->gfx_level >= GFX10)
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gpu_info->num_physical_wave64_vgprs_per_simd = 512;
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else
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gpu_info->num_physical_wave64_vgprs_per_simd = 256;
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gpu_info->num_simd_per_compute_unit = gpu_info->gfx_level >= GFX10 ? 2 : 4;
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gpu_info->lds_size_per_workgroup = gpu_info->gfx_level >= GFX7 ? 64 * 1024 : 32 * 1024;
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gpu_info->max_render_backends = pci_ids[gpu_info->family].num_render_backends;
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gpu_info->has_dedicated_vram = pci_ids[gpu_info->family].has_dedicated_vram;
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gpu_info->has_packed_math_16bit = gpu_info->gfx_level >= GFX9;
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gpu_info->has_image_load_dcc_bug = gpu_info->family == CHIP_NAVI23 || gpu_info->family == CHIP_VANGOGH;
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gpu_info->has_distributed_tess =
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gpu_info->gfx_level >= GFX10 || (gpu_info->gfx_level >= GFX8 && gpu_info->max_se >= 2);
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gpu_info->has_accelerated_dot_product =
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gpu_info->family == CHIP_VEGA20 ||
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(gpu_info->family >= CHIP_MI100 && gpu_info->family != CHIP_NAVI10 && gpu_info->family != CHIP_GFX1013);
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gpu_info->has_image_bvh_intersect_ray = gpu_info->gfx_level >= GFX10_3 || gpu_info->family == CHIP_GFX1013;
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gpu_info->address32_hi = gpu_info->gfx_level >= GFX9 ? 0xffff8000u : 0x0;
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gpu_info->has_rbplus = gpu_info->family == CHIP_STONEY || gpu_info->gfx_level >= GFX9;
|
||||
gpu_info->rbplus_allowed =
|
||||
gpu_info->has_rbplus &&
|
||||
(gpu_info->family == CHIP_STONEY || gpu_info->family == CHIP_VEGA12 || gpu_info->family == CHIP_RAVEN ||
|
||||
gpu_info->family == CHIP_RAVEN2 || gpu_info->family == CHIP_RENOIR || gpu_info->gfx_level >= GFX10_3);
|
||||
|
||||
gpu_info->has_gang_submit = true;
|
||||
gpu_info->mesh_fast_launch_2 = gpu_info->gfx_level >= GFX11;
|
||||
gpu_info->hs_offchip_workgroup_dw_size = gpu_info->family == CHIP_HAWAII ? 4096 : 8192;
|
||||
gpu_info->has_ls_vgpr_init_bug = gpu_info->family == CHIP_VEGA10 || gpu_info->family == CHIP_RAVEN;
|
||||
gpu_info->has_graphics = true;
|
||||
gpu_info->ip[AMD_IP_GFX].num_queues = 1;
|
||||
|
||||
gpu_info->gart_page_size = 4096;
|
||||
}
|
||||
|
||||
static void
|
||||
radv_null_winsys_destroy(struct radeon_winsys *rws)
|
||||
{
|
||||
FREE(rws);
|
||||
}
|
||||
|
||||
static int
|
||||
radv_null_winsys_get_fd(struct radeon_winsys *rws)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
static const struct vk_sync_type *const *
|
||||
radv_null_winsys_get_sync_types(struct radeon_winsys *rws)
|
||||
{
|
||||
return radv_null_winsys(rws)->sync_types;
|
||||
}
|
||||
|
||||
static struct util_sync_provider *
|
||||
radv_null_winsys_get_sync_provider(struct radeon_winsys *rws)
|
||||
{
|
||||
return radv_null_winsys(rws)->sync_provider;
|
||||
}
|
||||
|
||||
struct radeon_winsys *
|
||||
radv_null_winsys_create()
|
||||
{
|
||||
struct radv_null_winsys *ws;
|
||||
|
||||
ws = calloc(1, sizeof(struct radv_null_winsys));
|
||||
if (!ws)
|
||||
return NULL;
|
||||
|
||||
ws->base.destroy = radv_null_winsys_destroy;
|
||||
ws->base.query_info = radv_null_winsys_query_info;
|
||||
ws->base.get_fd = radv_null_winsys_get_fd;
|
||||
ws->base.get_sync_types = radv_null_winsys_get_sync_types;
|
||||
ws->base.get_sync_provider = radv_null_winsys_get_sync_provider;
|
||||
radv_null_bo_init_functions(ws);
|
||||
radv_null_cs_init_functions(ws);
|
||||
|
||||
ws->sync_types[0] = &vk_sync_dummy_type;
|
||||
ws->sync_types[1] = NULL;
|
||||
ws->sync_provider = util_sync_provider_drm(-1);
|
||||
return &ws->base;
|
||||
}
|
||||
@@ -1,33 +0,0 @@
|
||||
/*
|
||||
* Copyright © 2016 Red Hat.
|
||||
* Copyright © 2016 Bas Nieuwenhuizen
|
||||
* based on amdgpu winsys.
|
||||
* Copyright © 2011 Marek Olšák <maraeo@gmail.com>
|
||||
* Copyright © 2015 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*/
|
||||
|
||||
#ifndef RADV_NULL_WINSYS_H
|
||||
#define RADV_NULL_WINSYS_H
|
||||
|
||||
#include "util/list.h"
|
||||
#include "ac_gpu_info.h"
|
||||
#include "radv_radeon_winsys.h"
|
||||
|
||||
struct vk_sync_type;
|
||||
struct util_sync_provider;
|
||||
|
||||
struct radv_null_winsys {
|
||||
struct radeon_winsys base;
|
||||
const struct vk_sync_type *sync_types[2];
|
||||
struct util_sync_provider *sync_provider;
|
||||
};
|
||||
|
||||
static inline struct radv_null_winsys *
|
||||
radv_null_winsys(struct radeon_winsys *base)
|
||||
{
|
||||
return (struct radv_null_winsys *)base;
|
||||
}
|
||||
|
||||
#endif /* RADV_NULL_WINSYS_H */
|
||||
@@ -1,16 +0,0 @@
|
||||
/*
|
||||
* Copyright © 2020 Valve Corporation
|
||||
*
|
||||
* based on amdgpu winsys.
|
||||
* Copyright © 2016 Red Hat.
|
||||
* Copyright © 2016 Bas Nieuwenhuizen
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*/
|
||||
|
||||
#ifndef RADV_NULL_WINSYS_PUBLIC_H
|
||||
#define RADV_NULL_WINSYS_PUBLIC_H
|
||||
|
||||
struct radeon_winsys *radv_null_winsys_create(void);
|
||||
|
||||
#endif /* RADV_NULL_WINSYS_PUBLIC_H */
|
||||
Reference in New Issue
Block a user