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radeonsi: fix a depth texturing performance regression on gfx6-7

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Fixes: 0580d4c1 "radeonsi: enable HTILE with mipmapping on gfx9+"
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5398

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13048>
This commit is contained in:
Marek Olšák
2021-09-25 04:53:47 -04:00
committed by Marge Bot
parent eb06e6e6cd
commit 4cb008719c
1 changed files with 13 additions and 1 deletions
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src/gallium/drivers/radeonsi/si_pipe.h
+13 -1
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@@ -1765,7 +1765,19 @@ static inline bool si_htile_enabled(struct si_texture *tex, unsigned level, unsi
if (zs_mask == PIPE_MASK_S && (tex->htile_stencil_disabled || !tex->surface.has_stencil))
return false;
return tex->is_depth && tex->surface.meta_offset && level < tex->surface.num_meta_levels;
if (!tex->is_depth || !tex->surface.meta_offset)
return false;
struct si_screen *sscreen = (struct si_screen *)tex->buffer.b.b.screen;
if (sscreen->info.chip_class >= GFX8) {
return level < tex->surface.num_meta_levels;
} else {
/* GFX6-7 don't have TC-compatible HTILE, which means they have to run
* a decompression pass for every mipmap level before texturing, so compress
* only one level to reduce the number of decompression passes to a minimum.
*/
return level == 0;
}
}
static inline bool vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level,