crocus: Reduce SSBO alignment requirements from 64B to 4B.
Mirroring a change in iris; see the previous commit for rationale. One difference is that crocus does sometimes use CPU maps on Atoms for *reads*...but writes don't go through CPU caches. Should be OK. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11727>
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@@ -305,14 +305,7 @@ crocus_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
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return CROCUS_MAP_BUFFER_ALIGNMENT;
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case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
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/* Choose a cacheline (64 bytes) so that we can safely have the CPU and
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* GPU writing the same SSBO on non-coherent systems (Atom CPUs). With
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* UBOs, the GPU never writes, so there's no problem. For an SSBO, the
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* GPU and the CPU can be updating disjoint regions of the buffer
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* simultaneously and that will break if the regions overlap the same
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* cacheline.
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*/
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return devinfo->ver >= 7 ? 64 : 0;
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return devinfo->ver >= 7 ? 4 : 0;
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case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
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return devinfo->ver >= 7 ? (1 << 27) : 0;
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case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
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