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i965: drop likely/unlikely around INTEL_DEBUG

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It's included in declaration of INTEL_DEBUG.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6732>
This commit is contained in:
Marcin Ślusarz
2020-09-14 18:52:02 +02:00
committed by Marge Bot
parent e6d26fbf3d
commit 4b9e38ca06
16 changed files with 27 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/mesa/drivers/dri/i965/brw_clear.c
+1 -1
View File
@@ -63,7 +63,7 @@ debug_mask(const char *name, GLbitfield mask)
{
GLuint i;
if (unlikely(INTEL_DEBUG & DEBUG_BLIT)) {
if (INTEL_DEBUG & DEBUG_BLIT) {
DBG("%s clear:", name);
for (i = 0; i < BUFFER_COUNT; i++) {
if (mask & (1 << i))
src/mesa/drivers/dri/i965/brw_context.c
+3 -3
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@@ -1459,7 +1459,7 @@ intel_update_dri2_buffers(struct brw_context *brw, __DRIdrawable *drawable)
* thus ignore the invalidate. */
drawable->lastStamp = drawable->dri2.stamp;
if (unlikely(INTEL_DEBUG & DEBUG_DRI))
if (INTEL_DEBUG & DEBUG_DRI)
fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable);
intel_query_dri2_buffers(brw, drawable, &buffers, &count);
@@ -1512,7 +1512,7 @@ intel_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
* thus ignore the invalidate. */
drawable->lastStamp = drawable->dri2.stamp;
if (unlikely(INTEL_DEBUG & DEBUG_DRI))
if (INTEL_DEBUG & DEBUG_DRI)
fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable);
if (dri_screen->image.loader)
@@ -1691,7 +1691,7 @@ intel_process_dri2_buffer(struct brw_context *brw,
if (old_name == buffer->name)
return;
if (unlikely(INTEL_DEBUG & DEBUG_DRI)) {
if (INTEL_DEBUG & DEBUG_DRI) {
fprintf(stderr,
"attaching buffer %d, at %d, cpp %d, pitch %d\n",
buffer->name, buffer->attachment,
src/mesa/drivers/dri/i965/brw_context.h
+1 -1
View File
@@ -388,7 +388,7 @@ struct brw_cache {
#define perf_debug(...) do { \
static GLuint msg_id = 0; \
if (unlikely(INTEL_DEBUG & DEBUG_PERF)) \
if (INTEL_DEBUG & DEBUG_PERF) \
dbg_printf(__VA_ARGS__); \
if (brw->perf_debug) \
_mesa_gl_debugf(&brw->ctx, &msg_id, \
src/mesa/drivers/dri/i965/brw_draw_upload.c
+1 -1
View File
@@ -256,7 +256,7 @@ brw_get_vertex_surface_type(struct brw_context *brw,
const bool is_ivybridge_or_older =
devinfo->gen <= 7 && !devinfo->is_baytrail && !devinfo->is_haswell;
if (unlikely(INTEL_DEBUG & DEBUG_VERTS))
if (INTEL_DEBUG & DEBUG_VERTS)
fprintf(stderr, "type %s size %d normalized %d\n",
_mesa_enum_to_string(glformat->Type),
glformat->Size, glformat->Normalized);
src/mesa/drivers/dri/i965/brw_ff_gs.c
+1 -1
View File
@@ -133,7 +133,7 @@ brw_codegen_ff_gs_prog(struct brw_context *brw,
*/
program = brw_get_program(&c.func, &program_size);
if (unlikely(INTEL_DEBUG & DEBUG_GS)) {
if (INTEL_DEBUG & DEBUG_GS) {
fprintf(stderr, "gs:\n");
brw_disassemble_with_labels(&brw->screen->devinfo, c.func.store,
0, program_size, stderr);
src/mesa/drivers/dri/i965/brw_state_upload.c
+3 -3
View File
@@ -620,7 +620,7 @@ brw_upload_pipeline_state(struct brw_context *brw,
if (pipeline == BRW_RENDER_PIPELINE && brw->current_hash_scale != 1)
brw_emit_hashing_mode(brw, UINT_MAX, UINT_MAX, 1);
if (unlikely(INTEL_DEBUG & DEBUG_REEMIT)) {
if (INTEL_DEBUG & DEBUG_REEMIT) {
/* Always re-emit all state. */
brw->NewGLState = ~0;
ctx->NewDriverState = ~0ull;
@@ -690,7 +690,7 @@ brw_upload_pipeline_state(struct brw_context *brw,
brw_get_pipeline_atoms(brw, pipeline);
const int num_atoms = brw->num_atoms[pipeline];
if (unlikely(INTEL_DEBUG)) {
if (INTEL_DEBUG) {
/* Debug version which enforces various sanity checks on the
* state flags which are generated and checked to help ensure
* state atoms are ordered correctly in the list.
@@ -724,7 +724,7 @@ brw_upload_pipeline_state(struct brw_context *brw,
}
}
if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
if (INTEL_DEBUG & DEBUG_STATE) {
STATIC_ASSERT(ARRAY_SIZE(brw_bits) == BRW_NUM_STATE_BITS + 1);
brw_update_dirty_count(mesa_bits, state.mesa);
src/mesa/drivers/dri/i965/brw_tcs.c
+1 -1
View File
@@ -98,7 +98,7 @@ brw_codegen_tcs_prog(struct brw_context *brw, struct brw_program *tcp,
}
int st_index = -1;
if (unlikely((INTEL_DEBUG & DEBUG_SHADER_TIME) && tep))
if (((INTEL_DEBUG & DEBUG_SHADER_TIME) && tep))
st_index = brw_get_shader_time_index(brw, &tep->program, ST_TCS, true);
if (unlikely(brw->perf_debug)) {
src/mesa/drivers/dri/i965/brw_tes.c
+1 -1
View File
@@ -61,7 +61,7 @@ brw_codegen_tes_prog(struct brw_context *brw,
prog_data.base.base.ubo_ranges);
int st_index = -1;
if (unlikely(INTEL_DEBUG & DEBUG_SHADER_TIME))
if (INTEL_DEBUG & DEBUG_SHADER_TIME)
st_index = brw_get_shader_time_index(brw, &tep->program, ST_TES, true);
if (unlikely(brw->perf_debug)) {
src/mesa/drivers/dri/i965/brw_urb.c
+2 -2
View File
@@ -189,12 +189,12 @@ brw_calculate_urb_fence(struct brw_context *brw, unsigned csize,
exit(1);
}
if (unlikely(INTEL_DEBUG & (DEBUG_URB|DEBUG_PERF)))
if (INTEL_DEBUG & (DEBUG_URB|DEBUG_PERF))
fprintf(stderr, "URB CONSTRAINED\n");
}
done:
if (unlikely(INTEL_DEBUG & DEBUG_URB))
if (INTEL_DEBUG & DEBUG_URB)
fprintf(stderr,
"URB fence: %d ..VS.. %d ..GS.. %d ..CLP.. %d ..SF.. %d ..CS.. %d\n",
brw->urb.vs_start,
src/mesa/drivers/dri/i965/brw_vs.c
+1 -1
View File
@@ -171,7 +171,7 @@ brw_codegen_vs_prog(struct brw_context *brw,
start_time = get_time();
}
if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
if (INTEL_DEBUG & DEBUG_VS) {
if (vp->program.is_arb_asm)
brw_dump_arb_asm("vertex", &vp->program);
}
src/mesa/drivers/dri/i965/brw_wm.c
+2 -2
View File
@@ -99,7 +99,7 @@ brw_codegen_wm_prog(struct brw_context *brw,
} else {
brw_nir_setup_arb_uniforms(mem_ctx, nir, &fp->program, &prog_data.base);
if (unlikely(INTEL_DEBUG & DEBUG_WM))
if (INTEL_DEBUG & DEBUG_WM)
brw_dump_arb_asm("fragment", &fp->program);
}
@@ -153,7 +153,7 @@ brw_codegen_wm_prog(struct brw_context *brw,
brw_alloc_stage_scratch(brw, &brw->wm.base, prog_data.base.total_scratch);
if (unlikely((INTEL_DEBUG & DEBUG_WM) && fp->program.is_arb_asm))
if (((INTEL_DEBUG & DEBUG_WM) && fp->program.is_arb_asm))
fprintf(stderr, "\n");
/* The param and pull_param arrays will be freed by the shader cache. */
src/mesa/drivers/dri/i965/gen7_l3_state.c
+1 -1
View File
@@ -242,7 +242,7 @@ brw_emit_l3_state(struct brw_context *brw)
update_urb_size(brw, cfg);
brw->l3.config = cfg;
if (unlikely(INTEL_DEBUG & DEBUG_L3)) {
if (INTEL_DEBUG & DEBUG_L3) {
fprintf(stderr, "L3 config transition (%f > %f): ", dw, dw_threshold);
gen_dump_l3_config(cfg, stderr);
}
src/mesa/drivers/dri/i965/intel_batchbuffer.c
+5 -5
View File
@@ -130,7 +130,7 @@ intel_batchbuffer_init(struct brw_context *brw)
struct intel_batchbuffer *batch = &brw->batch;
const struct gen_device_info *devinfo = &screen->devinfo;
if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
if (INTEL_DEBUG & DEBUG_BATCH) {
/* The shadow doesn't get relocs written so state decode fails. */
batch->use_shadow_copy = false;
} else
@@ -830,7 +830,7 @@ submit_batch(struct brw_context *brw, int in_fence_fd, int *out_fence_fd)
throttle(brw);
}
if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
if (INTEL_DEBUG & DEBUG_BATCH) {
gen_print_batch(&batch->decoder, batch->batch.map,
4 * USED_BATCH(*batch),
batch->batch.bo->gtt_offset, false);
@@ -879,7 +879,7 @@ _intel_batchbuffer_flush_fence(struct brw_context *brw,
brw_bo_reference(brw->throttle_batch[0]);
}
if (unlikely(INTEL_DEBUG & (DEBUG_BATCH | DEBUG_SUBMIT))) {
if (INTEL_DEBUG & (DEBUG_BATCH | DEBUG_SUBMIT)) {
int bytes_for_commands = 4 * USED_BATCH(brw->batch);
int bytes_for_state = brw->batch.state_used;
fprintf(stderr, "%19s:%-3d: Batchbuffer flush with %5db (%0.1f%%) (pkt),"
@@ -897,7 +897,7 @@ _intel_batchbuffer_flush_fence(struct brw_context *brw,
ret = submit_batch(brw, in_fence_fd, out_fence_fd);
if (unlikely(INTEL_DEBUG & DEBUG_SYNC)) {
if (INTEL_DEBUG & DEBUG_SYNC) {
fprintf(stderr, "waiting for idle\n");
brw_bo_wait_rendering(brw->batch.batch.bo);
}
@@ -1067,7 +1067,7 @@ brw_state_batch(struct brw_context *brw,
assert(offset + size < batch->state.bo->size);
}
if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
if (INTEL_DEBUG & DEBUG_BATCH) {
_mesa_hash_table_u64_insert(batch->state_batch_sizes,
offset, (void *) (uintptr_t) size);
}
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+1 -1
View File
@@ -170,7 +170,7 @@ intel_miptree_choose_aux_usage(struct brw_context *brw,
if (_mesa_is_format_color_format(mt->format)) {
if (mt->surf.samples > 1) {
mt->aux_usage = ISL_AUX_USAGE_MCS;
} else if (!unlikely(INTEL_DEBUG & DEBUG_NO_RBC) &&
} else if (!(INTEL_DEBUG & DEBUG_NO_RBC) &&
format_supports_ccs_e(brw, mt->format)) {
mt->aux_usage = ISL_AUX_USAGE_CCS_E;
} else if (brw->mesa_format_supports_render[mt->format]) {
src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
+1 -1
View File
@@ -309,7 +309,7 @@ do_blit_bitmap( struct gl_context *ctx,
}
out:
if (unlikely(INTEL_DEBUG & DEBUG_SYNC))
if (INTEL_DEBUG & DEBUG_SYNC)
intel_batchbuffer_flush(brw);
if (unpack->BufferObj) {
src/mesa/drivers/dri/i965/intel_screen.c
+2 -2
View File
@@ -367,7 +367,7 @@ modifier_is_supported(const struct gen_device_info *devinfo,
if (modinfo->aux_usage == ISL_AUX_USAGE_CCS_E) {
/* If INTEL_DEBUG=norbc is set, don't support any CCS_E modifiers */
if (unlikely(INTEL_DEBUG & DEBUG_NO_RBC))
if (INTEL_DEBUG & DEBUG_NO_RBC)
return false;
/* CCS_E is not supported for planar images */
@@ -2499,7 +2499,7 @@ shader_perf_log_mesa(void *data, const char *fmt, ...)
va_list args;
va_start(args, fmt);
if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
if (INTEL_DEBUG & DEBUG_PERF) {
va_list args_copy;
va_copy(args_copy, args);
vfprintf(stderr, fmt, args_copy);