AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

freedreno/a6xx: fix shaders w/ >= 24 regs

Browse Source 
Possibly these bits mean something else now.  Blob always seems to use
FOUR_QUADS, and changing to TWO_QUADS seems to cause different threads
to overlap registers.

Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark
2018-09-12 15:54:47 -04:00
parent 6530fcc4a7
commit 49d22c2dfc
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/freedreno/a6xx/fd6_program.c
+1 -1
View File
@@ -310,7 +310,7 @@ fd6_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
setup_stages(emit, s);
fssz = (s[FS].i->max_reg >= 24) ? TWO_QUADS : FOUR_QUADS;
fssz = FOUR_QUADS;
pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);