fix segfault with ATI_fs when trying to use a not enabled texture unit (bug #9110).
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@@ -362,7 +362,7 @@ static void r200UpdateFSRouting( GLcontext *ctx ) {
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if (shader->NumPasses < 2) {
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for (reg = 0; reg < R200_MAX_TEXTURE_UNITS; reg++) {
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struct gl_texture_object *texObj = ctx->Texture.Unit[reg]._Current;
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GLbitfield targetbit = ctx->Texture.Unit[reg]._ReallyEnabled;
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R200_STATECHANGE( rmesa, tex[reg] );
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rmesa->hw.tex[reg].cmd[TEX_PP_TXMULTI_CTL] = 0;
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if (shader->SetupInst[0][reg].Opcode) {
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@@ -385,15 +385,16 @@ static void r200UpdateFSRouting( GLcontext *ctx ) {
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else {
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txformat_x |= R200_TEXCOORD_PROJ;
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}
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rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg;
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}
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else if (texObj->Target == GL_TEXTURE_3D) {
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else if (targetbit == TEXTURE_3D_BIT) {
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txformat_x |= R200_TEXCOORD_VOLUME;
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}
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else if (texObj->Target == GL_TEXTURE_CUBE_MAP) {
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else if (targetbit == TEXTURE_CUBE_BIT) {
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txformat_x |= R200_TEXCOORD_CUBIC_ENV;
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}
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else if (shader->SetupInst[0][reg].swizzle == GL_SWIZZLE_STR_ATI ||
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shader->SetupInst[0][reg].swizzle == GL_SWIZZLE_STQ_ATI) {
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shader->SetupInst[0][reg].swizzle == GL_SWIZZLE_STQ_ATI) {
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txformat_x |= R200_TEXCOORD_NONPROJ;
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}
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else {
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@@ -401,16 +402,16 @@ static void r200UpdateFSRouting( GLcontext *ctx ) {
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}
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rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT] = txformat;
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rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT_X] = txformat_x;
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/* is this a good idea? Could potentially sample from not enabled unit.
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results are probably undefined anyway (?) but I hope it doesn't lock up... */
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rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg;
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/* enabling texturing when unit isn't correctly configured may not be safe */
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if (targetbit)
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rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg;
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}
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}
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} else {
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/* setup 1st pass */
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for (reg = 0; reg < R200_MAX_TEXTURE_UNITS; reg++) {
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struct gl_texture_object *texObj = ctx->Texture.Unit[reg]._Current;
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GLbitfield targetbit = ctx->Texture.Unit[reg]._ReallyEnabled;
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R200_STATECHANGE( rmesa, tex[reg] );
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GLuint txformat_multi = 0;
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if (shader->SetupInst[0][reg].Opcode) {
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@@ -425,11 +426,12 @@ static void r200UpdateFSRouting( GLcontext *ctx ) {
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else {
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txformat_multi |= R200_PASS1_TEXCOORD_PROJ;
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}
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rmesa->hw.cst.cmd[CST_PP_CNTL_X] |= R200_PPX_TEX_0_ENABLE << reg;
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}
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else if (texObj->Target == GL_TEXTURE_3D) {
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else if (targetbit == TEXTURE_3D_BIT) {
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txformat_multi |= R200_PASS1_TEXCOORD_VOLUME;
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}
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else if (texObj->Target == GL_TEXTURE_CUBE_MAP) {
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else if (targetbit == TEXTURE_CUBE_BIT) {
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txformat_multi |= R200_PASS1_TEXCOORD_CUBIC_ENV;
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}
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else if (shader->SetupInst[0][reg].swizzle == GL_SWIZZLE_STR_ATI ||
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@@ -439,14 +441,15 @@ static void r200UpdateFSRouting( GLcontext *ctx ) {
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else {
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txformat_multi |= R200_PASS1_TEXCOORD_PROJ;
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}
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rmesa->hw.cst.cmd[CST_PP_CNTL_X] |= R200_PPX_TEX_0_ENABLE << reg;
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if (targetbit)
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rmesa->hw.cst.cmd[CST_PP_CNTL_X] |= R200_PPX_TEX_0_ENABLE << reg;
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}
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rmesa->hw.tex[reg].cmd[TEX_PP_TXMULTI_CTL] = txformat_multi;
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}
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/* setup 2nd pass */
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for (reg=0; reg < R200_MAX_TEXTURE_UNITS; reg++) {
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struct gl_texture_object *texObj = ctx->Texture.Unit[reg]._Current;
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GLbitfield targetbit = ctx->Texture.Unit[reg]._ReallyEnabled;
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if (shader->SetupInst[1][reg].Opcode) {
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GLuint coord = shader->SetupInst[1][reg].src;
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GLuint txformat = rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT]
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@@ -463,15 +466,16 @@ static void r200UpdateFSRouting( GLcontext *ctx ) {
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else {
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txformat_x |= R200_TEXCOORD_PROJ;
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}
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rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg;
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}
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else if (texObj->Target == GL_TEXTURE_3D) {
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else if (targetbit == TEXTURE_3D_BIT) {
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txformat_x |= R200_TEXCOORD_VOLUME;
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}
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else if (texObj->Target == GL_TEXTURE_CUBE_MAP) {
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else if (targetbit == TEXTURE_CUBE_BIT) {
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txformat_x |= R200_TEXCOORD_CUBIC_ENV;
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}
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else if (shader->SetupInst[1][reg].swizzle == GL_SWIZZLE_STR_ATI ||
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shader->SetupInst[1][reg].swizzle == GL_SWIZZLE_STQ_ATI) {
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shader->SetupInst[1][reg].swizzle == GL_SWIZZLE_STQ_ATI) {
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txformat_x |= R200_TEXCOORD_NONPROJ;
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}
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else {
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@@ -488,7 +492,8 @@ static void r200UpdateFSRouting( GLcontext *ctx ) {
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}
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rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT_X] = txformat_x;
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rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT] = txformat;
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rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg;
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if (targetbit)
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rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg;
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}
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}
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}
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