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intel/brw: Change unit tests to use TEX_LOGICAL instead of TEX

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We're not really doing any fancy texturing here, just emitting a TEX
instruction that writes multiple destination registers.  I plan to
remove the non-logical TEX instruction in the next commit, so we swap
these over to use the logical version instead.  It should work just as
well for the purposes of the test.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27908>
This commit is contained in:
Kenneth Graunke
2024-02-28 23:34:28 -08:00
committed by Marge Bot
parent e03e593143
commit 494eee1337
2 changed files with 20 additions and 4 deletions
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12
src/intel/compiler/test_fs_cmod_propagation.cpp
View File

@@ -449,8 +449,16 @@ TEST_F(cmod_propagation_test, intervening_dest_write)
fs_reg src1 = v->vgrf(glsl_float_type());
fs_reg src2 = v->vgrf(glsl_vec2_type());
fs_reg zero(brw_imm_f(0.0f));
fs_reg tex_srcs[TEX_LOGICAL_NUM_SRCS];
tex_srcs[TEX_LOGICAL_SRC_COORDINATE] = src2;
tex_srcs[TEX_LOGICAL_SRC_SURFACE] = brw_imm_ud(0);
tex_srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = brw_imm_ud(2);
tex_srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = brw_imm_ud(0);
tex_srcs[TEX_LOGICAL_SRC_RESIDENCY] = brw_imm_ud(0);
bld.ADD(offset(dest, bld, 2), src0, src1);
bld.emit(SHADER_OPCODE_TEX, dest, src2)
bld.emit(SHADER_OPCODE_TEX_LOGICAL, dest, tex_srcs, TEX_LOGICAL_NUM_SRCS)
->size_written = 4 * REG_SIZE;
bld.CMP(bld.null_reg_f(), offset(dest, bld, 2), zero, BRW_CONDITIONAL_GE);
@@ -475,7 +483,7 @@ TEST_F(cmod_propagation_test, intervening_dest_write)
EXPECT_EQ(2, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(SHADER_OPCODE_TEX, instruction(block0, 1)->opcode);
EXPECT_EQ(SHADER_OPCODE_TEX_LOGICAL, instruction(block0, 1)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod);

12
src/intel/compiler/test_fs_saturate_propagation.cpp
View File

@@ -653,8 +653,16 @@ TEST_F(saturate_propagation_test, intervening_dest_write)
fs_reg src0 = v->vgrf(glsl_float_type());
fs_reg src1 = v->vgrf(glsl_float_type());
fs_reg src2 = v->vgrf(glsl_vec2_type());
fs_reg tex_srcs[TEX_LOGICAL_NUM_SRCS];
tex_srcs[TEX_LOGICAL_SRC_COORDINATE] = src2;
tex_srcs[TEX_LOGICAL_SRC_SURFACE] = brw_imm_ud(0);
tex_srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = brw_imm_ud(2);
tex_srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = brw_imm_ud(0);
tex_srcs[TEX_LOGICAL_SRC_RESIDENCY] = brw_imm_ud(0);
bld.ADD(offset(dst0, bld, 2), src0, src1);
bld.emit(SHADER_OPCODE_TEX, dst0, src2)
bld.emit(SHADER_OPCODE_TEX_LOGICAL, dst0, tex_srcs, TEX_LOGICAL_NUM_SRCS)
->size_written = 8 * REG_SIZE;
set_saturate(true, bld.MOV(dst1, offset(dst0, bld, 2)));
@@ -679,7 +687,7 @@ TEST_F(saturate_propagation_test, intervening_dest_write)
EXPECT_EQ(2, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_FALSE(instruction(block0, 0)->saturate);
EXPECT_EQ(SHADER_OPCODE_TEX, instruction(block0, 1)->opcode);
EXPECT_EQ(SHADER_OPCODE_TEX_LOGICAL, instruction(block0, 1)->opcode);
EXPECT_FALSE(instruction(block0, 0)->saturate);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 2)->opcode);
EXPECT_TRUE(instruction(block0, 2)->saturate);