freedreno/ir3: all mem instructions have WAR hazzard

It isn't just load instructions that have write-after-read hazzard.

Fixes stk gaussian blur compute shaders.

Signed-off-by: Rob Clark <robdclark@gmail.com>

src/gallium/drivers/freedreno/ir3/ir3_legalize.c

@@ -211,7 +211,7 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block)
 		/* both tex/sfu appear to not always immediately consume
 		 * their src register(s):
 		 */
-		if (is_tex(n) || is_sfu(n) || is_load(n)) {
+		if (is_tex(n) || is_sfu(n) || is_mem(n)) {
 			foreach_src(reg, n) {
 				if (reg_gpr(reg))
 					regmask_set(&needs_ss_war, reg);