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radv: rework emitting SPI_SHADER_Z_FORMAT

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This fixes a small issue when the Z format in PS epilogs change, like
when alpha-to-coverage is enabled and then disabled.

igned-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32675>
This commit is contained in:
Samuel Pitoiset
2024-12-17 09:00:13 +01:00
committed by Marge Bot
parent 28a214728c
commit 47dc9ca512
5 changed files with 15 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
src/amd/vulkan/radv_cmd_buffer.c
View File

@@ -1945,14 +1945,6 @@ radv_emit_ps_epilog_state(struct radv_cmd_buffer *cmd_buffer, struct radv_shader
if (cmd_buffer->state.emitted_ps_epilog == ps_epilog)
return;
if (ps_epilog->spi_shader_z_format) {
if (pdev->info.gfx_level >= GFX12) {
radeon_set_context_reg(cmd_buffer->cs, R_028650_SPI_SHADER_Z_FORMAT, ps_epilog->spi_shader_z_format);
} else {
radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT, ps_epilog->spi_shader_z_format);
}
}
assert(ps_shader->config.num_shared_vgprs == 0);
if (G_00B848_VGPRS(ps_epilog->rsrc1) > G_00B848_VGPRS(ps_shader->config.rsrc1)) {
uint32_t rsrc1 = ps_shader->config.rsrc1;
@@ -2632,8 +2624,6 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer)
radeon_opt_set_context_reg(cmd_buffer, R_028640_SPI_PS_IN_CONTROL, RADV_TRACKED_SPI_PS_IN_CONTROL,
ps->info.regs.ps.spi_ps_in_control);
radeon_set_context_reg(cmd_buffer->cs, R_028650_SPI_SHADER_Z_FORMAT, ps->info.regs.ps.spi_shader_z_format);
radeon_set_context_reg(cmd_buffer->cs, R_028BBC_PA_SC_HISZ_CONTROL, ps->info.regs.ps.pa_sc_hisz_control);
} else {
radeon_opt_set_context_reg2(cmd_buffer, R_0286CC_SPI_PS_INPUT_ENA, RADV_TRACKED_SPI_PS_INPUT_ENA,
@@ -2644,9 +2634,6 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer)
ps->info.regs.ps.spi_ps_in_control);
}
radeon_opt_set_context_reg(cmd_buffer, R_028710_SPI_SHADER_Z_FORMAT, RADV_TRACKED_SPI_SHADER_Z_FORMAT,
ps->info.regs.ps.spi_shader_z_format);
if (pdev->info.gfx_level >= GFX9 && pdev->info.gfx_level < GFX11)
radeon_opt_set_context_reg(cmd_buffer, R_028C40_PA_SC_SHADER_CONTROL, RADV_TRACKED_PA_SC_SHADER_CONTROL,
ps->info.regs.ps.pa_sc_shader_control);
@@ -7805,10 +7792,12 @@ radv_bind_color_output_state(struct radv_cmd_buffer *cmd_buffer, const struct ra
{
const struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
uint32_t col_format = 0, cb_shader_mask = 0;
uint32_t col_format = 0, z_format = 0, cb_shader_mask = 0;
if (ps) {
col_format = ps_epilog ? ps_epilog->spi_shader_col_format : ps->info.ps.spi_shader_col_format;
z_format = ps_epilog && ps->info.ps.exports_mrtz_via_epilog ? ps_epilog->spi_shader_z_format
: ps->info.regs.ps.spi_shader_z_format;
cb_shader_mask = ps_epilog ? ps_epilog->cb_shader_mask : ps->info.ps.cb_shader_mask;
}
@@ -7829,8 +7818,9 @@ radv_bind_color_output_state(struct radv_cmd_buffer *cmd_buffer, const struct ra
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RBPLUS;
}
if (cmd_buffer->state.cb_shader_mask != cb_shader_mask) {
if (cmd_buffer->state.cb_shader_mask != cb_shader_mask || cmd_buffer->state.spi_shader_z_format != z_format) {
cmd_buffer->state.cb_shader_mask = cb_shader_mask;
cmd_buffer->state.spi_shader_z_format = z_format;
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_COLOR_OUTPUT;
}
}
@@ -10634,10 +10624,14 @@ radv_emit_color_output_state(struct radv_cmd_buffer *cmd_buffer)
if (pdev->info.gfx_level >= GFX12) {
radeon_set_context_reg(cmd_buffer->cs, R_028854_CB_SHADER_MASK, cmd_buffer->state.cb_shader_mask);
radeon_set_context_reg(cmd_buffer->cs, R_028654_SPI_SHADER_COL_FORMAT, col_format_compacted);
radeon_set_context_reg_seq(cmd_buffer->cs, R_028650_SPI_SHADER_Z_FORMAT, 2);
radeon_emit(cmd_buffer->cs, cmd_buffer->state.spi_shader_z_format);
radeon_emit(cmd_buffer->cs, col_format_compacted); /* SPI_SHADER_COL_FORMAT */
} else {
radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, cmd_buffer->state.cb_shader_mask);
radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, col_format_compacted);
radeon_set_context_reg_seq(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT, 2);
radeon_emit(cmd_buffer->cs, cmd_buffer->state.spi_shader_z_format);
radeon_emit(cmd_buffer->cs, col_format_compacted); /* SPI_SHADER_COL_FORMAT */
}
cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_COLOR_OUTPUT;
@@ -13738,6 +13732,7 @@ radv_reset_pipeline_state(struct radv_cmd_buffer *cmd_buffer, VkPipelineBindPoin
cmd_buffer->state.last_vgt_shader = NULL;
cmd_buffer->state.emitted_vs_prolog = NULL;
cmd_buffer->state.spi_shader_col_format = 0;
cmd_buffer->state.spi_shader_z_format = 0;
cmd_buffer->state.cb_shader_mask = 0;
cmd_buffer->state.ms.sample_shading_enable = false;
cmd_buffer->state.ms.min_sample_shading = 1.0f;

1
src/amd/vulkan/radv_cmd_buffer.h
View File

@@ -459,6 +459,7 @@ struct radv_cmd_state {
unsigned tess_lds_size;
unsigned spi_shader_col_format;
unsigned spi_shader_z_format;
unsigned cb_shader_mask;
struct radv_multisample_state ms;

5
src/amd/vulkan/radv_pipeline_graphics.c
View File

@@ -1736,9 +1736,8 @@ radv_generate_ps_epilog_key(const struct radv_device *device, const struct radv_
key.color_map[1] = 1;
}
if (state->alpha_to_coverage_via_mrtz)
z_format = ac_get_spi_shader_z_format(state->export_depth, state->export_stencil, state->export_sample_mask,
state->alpha_to_coverage_via_mrtz);
z_format = ac_get_spi_shader_z_format(state->export_depth, state->export_stencil, state->export_sample_mask,
state->alpha_to_coverage_via_mrtz);
key.spi_shader_col_format = col_format;
key.color_is_int8 = pdev->info.gfx_level < GFX8 ? is_int8 : 0;

1
src/gallium/drivers/zink/ci/zink-radv-navi31-fails.txt
View File

@@ -173,7 +173,6 @@ spec@ext_framebuffer_multisample@interpolation 8 non-centroid-disabled,Fail
spec@arb_viewport_array@display-list,Fail
dEQP-GLES3.functional.shaders.precision.uint.highp_div_fragment,Fail
spec@arb_sample_shading@arb_sample_shading-builtin-gl-sample-mask-mrt-alpha-to-coverage,Fail
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-export,Fail
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-ownership_transfer,Fail

1
src/gallium/drivers/zink/ci/zink-radv-navi31-flakes.txt
View File

@@ -26,7 +26,6 @@ spec@!opengl 1.1@ppgtt_memory_alignment
spec@arb_compute_shader@local-id-explosion
spec@arb_depth_texture@fbo-depth-gl_depth_component16-blit
spec@arb_fragment_shader_interlock@arb_fragment_shader_interlock-image-load-store
spec@arb_sample_shading@arb_sample_shading-builtin-gl-sample-mask-mrt-alpha-to-coverage
spec@arb_sampler_objects@framebufferblit
spec@arb_shader_image_load_store@coherency
spec@arb_shader_image_load_store@coherency@Tessellation evaluation-Fragment shader/'coherent' qualifier coherency test/256x256