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radv: fix writing the alpha channel of MRT0 when alpha coverage is enabled

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This version is better and safer.

Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset
2019-02-18 17:42:10 +01:00
parent d6c43cceff
commit 47616810ed
1 changed files with 8 additions and 7 deletions
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src/amd/vulkan/radv_pipeline.c
+8 -7
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@@ -511,13 +511,6 @@ radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
cf = V_028714_SPI_SHADER_ZERO;
if (blend->need_src_alpha & (1 << i)) {
/* Write the alpha channel of MRT0 when alpha coverage is
* enabled because the depth attachment needs it.
*/
col_format |= V_028714_SPI_SHADER_32_ABGR;
}
} else {
struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
bool blend_enable =
@@ -531,6 +524,14 @@ radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
col_format |= cf << (4 * i);
}
if (!col_format && blend->need_src_alpha & (1 << 0)) {
/* When a subpass doesn't have any color attachments, write the
* alpha channel of MRT0 when alpha coverage is enabled because
* the depth attachment needs it.
*/
col_format |= V_028714_SPI_SHADER_32_ABGR;
}
/* If the i-th target format is set, all previous target formats must
* be non-zero to avoid hangs.
*/