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nv50/ir: add prefer_nir flag for getting compiler options

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So that we dont expose certain options for nir_to_tgsi

Signed-off-by: Yusuf Khan <yusiamerican@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19333>
This commit is contained in:
Yusuf Khan
2022-09-28 10:06:33 -05:00
committed by Marge Bot
parent def56b531c
commit 47251d2852
4 changed files with 75 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/gallium/drivers/nouveau/nv50/nv50_screen.c
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@@ -988,8 +988,9 @@ nv50_screen_get_compiler_options(struct pipe_screen *pscreen,
enum pipe_shader_ir ir,
enum pipe_shader_type shader)
{
struct nouveau_screen *screen = nouveau_screen(pscreen);
if (ir == PIPE_SHADER_IR_NIR)
return nv50_ir_nir_shader_compiler_options(NVISA_G80_CHIPSET, shader);
return nv50_ir_nir_shader_compiler_options(NVISA_G80_CHIPSET, shader, screen->prefer_nir);
return NULL;
}

2
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
View File

@@ -1020,7 +1020,7 @@ nvc0_screen_get_compiler_options(struct pipe_screen *pscreen,
struct nvc0_screen *screen = nvc0_screen(pscreen);
if (ir == PIPE_SHADER_IR_NIR)
return nv50_ir_nir_shader_compiler_options(screen->base.device->chipset,
shader);
shader, screen->base.prefer_nir);
return NULL;
}

2
src/nouveau/codegen/nv50_ir_driver.h
View File

@@ -220,7 +220,7 @@ extern "C" {
#endif
const struct nir_shader_compiler_options *
nv50_ir_nir_shader_compiler_options(int chipset, uint8_t shader_type);
nv50_ir_nir_shader_compiler_options(int chipset, uint8_t shader_type, bool prefer_nir);
extern int nv50_ir_generate_code(struct nv50_ir_prog_info *,
struct nv50_ir_prog_info_out *);

97
src/nouveau/codegen/nv50_ir_from_nir.cpp
View File

@@ -3438,7 +3438,7 @@ Program::makeFromNIR(struct nv50_ir_prog_info *info,
} // namespace nv50_ir
static nir_shader_compiler_options
nvir_nir_shader_compiler_options(int chipset, uint8_t shader_type)
nvir_nir_shader_compiler_options(int chipset, uint8_t shader_type, bool prefer_nir)
{
nir_shader_compiler_options op = {};
op.lower_fdiv = (chipset >= NVISA_GV100_CHIPSET);
@@ -3560,48 +3560,93 @@ nvir_nir_shader_compiler_options(int chipset, uint8_t shader_type)
}
static const nir_shader_compiler_options g80_nir_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_G80_CHIPSET, PIPE_SHADER_TYPES);
nvir_nir_shader_compiler_options(NVISA_G80_CHIPSET, PIPE_SHADER_TYPES, true);
static const nir_shader_compiler_options g80_fs_nir_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_G80_CHIPSET, PIPE_SHADER_FRAGMENT);
nvir_nir_shader_compiler_options(NVISA_G80_CHIPSET, PIPE_SHADER_FRAGMENT, true);
static const nir_shader_compiler_options gf100_nir_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GF100_CHIPSET, PIPE_SHADER_TYPES);
nvir_nir_shader_compiler_options(NVISA_GF100_CHIPSET, PIPE_SHADER_TYPES, true);
static const nir_shader_compiler_options gf100_fs_nir_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GF100_CHIPSET, PIPE_SHADER_FRAGMENT);
nvir_nir_shader_compiler_options(NVISA_GF100_CHIPSET, PIPE_SHADER_FRAGMENT, true);
static const nir_shader_compiler_options gm107_nir_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GM107_CHIPSET, PIPE_SHADER_TYPES);
nvir_nir_shader_compiler_options(NVISA_GM107_CHIPSET, PIPE_SHADER_TYPES, true);
static const nir_shader_compiler_options gm107_fs_nir_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GM107_CHIPSET, PIPE_SHADER_FRAGMENT);
nvir_nir_shader_compiler_options(NVISA_GM107_CHIPSET, PIPE_SHADER_FRAGMENT, true);
static const nir_shader_compiler_options gv100_nir_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GV100_CHIPSET, PIPE_SHADER_TYPES);
nvir_nir_shader_compiler_options(NVISA_GV100_CHIPSET, PIPE_SHADER_TYPES, true);
static const nir_shader_compiler_options gv100_fs_nir_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GV100_CHIPSET, PIPE_SHADER_FRAGMENT);
nvir_nir_shader_compiler_options(NVISA_GV100_CHIPSET, PIPE_SHADER_FRAGMENT, true);
static const nir_shader_compiler_options g80_tgsi_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_G80_CHIPSET, PIPE_SHADER_TYPES, false);
static const nir_shader_compiler_options g80_fs_tgsi_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_G80_CHIPSET, PIPE_SHADER_FRAGMENT, false);
static const nir_shader_compiler_options gf100_tgsi_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GF100_CHIPSET, PIPE_SHADER_TYPES, false);
static const nir_shader_compiler_options gf100_fs_tgsi_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GF100_CHIPSET, PIPE_SHADER_FRAGMENT, false);
static const nir_shader_compiler_options gm107_tgsi_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GM107_CHIPSET, PIPE_SHADER_TYPES, false);
static const nir_shader_compiler_options gm107_fs_tgsi_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GM107_CHIPSET, PIPE_SHADER_FRAGMENT, false);
static const nir_shader_compiler_options gv100_tgsi_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GV100_CHIPSET, PIPE_SHADER_TYPES, false);
static const nir_shader_compiler_options gv100_fs_tgsi_shader_compiler_options =
nvir_nir_shader_compiler_options(NVISA_GV100_CHIPSET, PIPE_SHADER_FRAGMENT, false);
const nir_shader_compiler_options *
nv50_ir_nir_shader_compiler_options(int chipset, uint8_t shader_type)
nv50_ir_nir_shader_compiler_options(int chipset, uint8_t shader_type, bool prefer_nir)
{
if (chipset >= NVISA_GV100_CHIPSET) {
if (shader_type == PIPE_SHADER_FRAGMENT)
return &gv100_fs_nir_shader_compiler_options;
else
return &gv100_nir_shader_compiler_options;
if (shader_type == PIPE_SHADER_FRAGMENT) {
if (prefer_nir)
return &gv100_fs_nir_shader_compiler_options;
else
return &gv100_fs_tgsi_shader_compiler_options;
} else {
if (prefer_nir)
return &gv100_nir_shader_compiler_options;
else
return &gv100_tgsi_shader_compiler_options;
}
}
if (chipset >= NVISA_GM107_CHIPSET) {
if (shader_type == PIPE_SHADER_FRAGMENT)
return &gm107_fs_nir_shader_compiler_options;
else
return &gm107_nir_shader_compiler_options;
if (shader_type == PIPE_SHADER_FRAGMENT) {
if (prefer_nir)
return &gm107_fs_nir_shader_compiler_options;
else
return &gm107_fs_tgsi_shader_compiler_options;
} else {
if (prefer_nir)
return &gm107_nir_shader_compiler_options;
else
return &gm107_tgsi_shader_compiler_options;
}
}
if (chipset >= NVISA_GF100_CHIPSET) {
if (shader_type == PIPE_SHADER_FRAGMENT)
return &gf100_fs_nir_shader_compiler_options;
else
return &gf100_nir_shader_compiler_options;
if (shader_type == PIPE_SHADER_FRAGMENT) {
if (prefer_nir)
return &gf100_fs_nir_shader_compiler_options;
else
return &gf100_fs_tgsi_shader_compiler_options;
} else {
if (prefer_nir)
return &gf100_nir_shader_compiler_options;
else
return &gf100_tgsi_shader_compiler_options;
}
}
if (shader_type == PIPE_SHADER_FRAGMENT)
return &g80_fs_nir_shader_compiler_options;
else
return &g80_nir_shader_compiler_options;
if (shader_type == PIPE_SHADER_FRAGMENT) {
if (prefer_nir)
return &g80_fs_nir_shader_compiler_options;
else
return &g80_fs_tgsi_shader_compiler_options;
} else {
if (prefer_nir)
return &g80_nir_shader_compiler_options;
else
return &g80_tgsi_shader_compiler_options;
}
}