i965: Make a brw_conditional_mod enum.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
@@ -117,7 +117,7 @@ brw_blorp_eu_emitter::emit_combine(enum opcode combine_opcode,
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}
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fs_inst *
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brw_blorp_eu_emitter::emit_cmp(int op,
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brw_blorp_eu_emitter::emit_cmp(enum brw_conditional_mod op,
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const struct brw_reg &x,
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const struct brw_reg &y)
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{
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@@ -59,7 +59,7 @@ protected:
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inline void emit_cond_mov(const struct brw_reg &x,
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const struct brw_reg &y,
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int op,
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enum brw_conditional_mod op,
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const struct brw_reg &dst,
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const struct brw_reg &src)
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{
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@@ -160,7 +160,7 @@ protected:
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_RNDD, dst, src));
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}
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inline void emit_cmp_if(int op,
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inline void emit_cmp_if(enum brw_conditional_mod op,
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const struct brw_reg &x,
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const struct brw_reg &y)
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{
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@@ -179,7 +179,8 @@ protected:
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}
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private:
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fs_inst *emit_cmp(int op, const struct brw_reg &x, const struct brw_reg &y);
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fs_inst *emit_cmp(enum brw_conditional_mod op, const struct brw_reg &x,
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const struct brw_reg &y);
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void *mem_ctx;
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exec_list insts;
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@@ -654,18 +654,20 @@ enum brw_compression {
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#define GEN6_COMPRESSION_1H 0
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#define GEN6_COMPRESSION_2H 2
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#define BRW_CONDITIONAL_NONE 0
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#define BRW_CONDITIONAL_Z 1
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#define BRW_CONDITIONAL_NZ 2
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#define BRW_CONDITIONAL_EQ 1 /* Z */
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#define BRW_CONDITIONAL_NEQ 2 /* NZ */
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#define BRW_CONDITIONAL_G 3
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#define BRW_CONDITIONAL_GE 4
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#define BRW_CONDITIONAL_L 5
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#define BRW_CONDITIONAL_LE 6
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#define BRW_CONDITIONAL_R 7
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#define BRW_CONDITIONAL_O 8
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#define BRW_CONDITIONAL_U 9
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enum PACKED brw_conditional_mod {
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BRW_CONDITIONAL_NONE = 0,
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BRW_CONDITIONAL_Z = 1,
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BRW_CONDITIONAL_NZ = 2,
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BRW_CONDITIONAL_EQ = 1, /* Z */
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BRW_CONDITIONAL_NEQ = 2, /* NZ */
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BRW_CONDITIONAL_G = 3,
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BRW_CONDITIONAL_GE = 4,
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BRW_CONDITIONAL_L = 5,
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BRW_CONDITIONAL_LE = 6,
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BRW_CONDITIONAL_R = 7,
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BRW_CONDITIONAL_O = 8,
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BRW_CONDITIONAL_U = 9,
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};
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#define BRW_DEBUG_NONE 0
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#define BRW_DEBUG_BREAKPOINT 1
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@@ -68,7 +68,7 @@ brw_reg_type_letters(unsigned type)
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/* Returns the corresponding conditional mod for swapping src0 and
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* src1 in e.g. CMP.
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*/
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uint32_t
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enum brw_conditional_mod
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brw_swap_cmod(uint32_t cmod)
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{
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switch (cmod) {
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@@ -320,7 +320,7 @@ void brw_shader_time_add(struct brw_compile *p,
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* channel.
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*/
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brw_inst *brw_IF(struct brw_compile *p, unsigned execute_size);
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brw_inst *gen6_IF(struct brw_compile *p, uint32_t conditional,
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brw_inst *gen6_IF(struct brw_compile *p, enum brw_conditional_mod conditional,
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struct brw_reg src0, struct brw_reg src1);
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void brw_ELSE(struct brw_compile *p);
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@@ -404,7 +404,7 @@ void brw_set_src1(struct brw_compile *p, brw_inst *insn, struct brw_reg reg);
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void brw_set_uip_jip(struct brw_compile *p);
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uint32_t brw_swap_cmod(uint32_t cmod);
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enum brw_conditional_mod brw_swap_cmod(uint32_t cmod);
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/* brw_eu_compact.c */
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void brw_init_compaction_tables(struct brw_context *brw);
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@@ -1241,7 +1241,7 @@ brw_IF(struct brw_compile *p, unsigned execute_size)
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* embedded comparison (conditional modifier). It is not used on gen7.
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*/
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brw_inst *
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gen6_IF(struct brw_compile *p, uint32_t conditional,
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gen6_IF(struct brw_compile *p, enum brw_conditional_mod conditional,
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struct brw_reg src0, struct brw_reg src1)
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{
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const struct brw_context *brw = p->brw;
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@@ -198,7 +198,8 @@ fs_visitor::IF(uint32_t predicate)
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/** Gen6 IF with embedded comparison. */
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fs_inst *
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fs_visitor::IF(const fs_reg &src0, const fs_reg &src1, uint32_t condition)
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fs_visitor::IF(const fs_reg &src0, const fs_reg &src1,
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enum brw_conditional_mod condition)
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{
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assert(brw->gen == 6);
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fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF,
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@@ -213,7 +214,8 @@ fs_visitor::IF(const fs_reg &src0, const fs_reg &src1, uint32_t condition)
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* the flag register with the packed 16 bits of the result.
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*/
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fs_inst *
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fs_visitor::CMP(fs_reg dst, fs_reg src0, fs_reg src1, uint32_t condition)
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fs_visitor::CMP(fs_reg dst, fs_reg src0, fs_reg src1,
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enum brw_conditional_mod condition)
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{
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fs_inst *inst;
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@@ -273,9 +273,10 @@ public:
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fs_inst *OR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
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fs_inst *XOR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
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fs_inst *IF(uint32_t predicate);
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fs_inst *IF(const fs_reg &src0, const fs_reg &src1, uint32_t condition);
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fs_inst *IF(const fs_reg &src0, const fs_reg &src1,
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enum brw_conditional_mod condition);
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fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
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uint32_t condition);
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enum brw_conditional_mod condition);
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fs_inst *LRP(const fs_reg &dst, const fs_reg &a, const fs_reg &y,
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const fs_reg &x);
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fs_inst *DEP_RESOLVE_MOV(int grf);
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@@ -385,7 +386,7 @@ public:
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fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
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void emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
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const fs_reg &a);
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void emit_minmax(uint32_t conditionalmod, const fs_reg &dst,
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void emit_minmax(enum brw_conditional_mod conditionalmod, const fs_reg &dst,
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const fs_reg &src0, const fs_reg &src1);
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bool try_emit_saturate(ir_expression *ir);
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bool try_emit_mad(ir_expression *ir);
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@@ -417,7 +418,7 @@ public:
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void emit_fp_minmax(const struct prog_instruction *fpi,
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fs_reg dst, fs_reg src0, fs_reg src1);
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void emit_fp_sop(uint32_t conditional_mod,
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void emit_fp_sop(enum brw_conditional_mod conditional_mod,
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const struct prog_instruction *fpi,
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fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
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@@ -442,7 +442,7 @@ try_constant_propagate(struct brw_context *brw, fs_inst *inst,
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inst->src[i] = entry->src;
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progress = true;
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} else if (i == 0 && inst->src[1].file != IMM) {
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uint32_t new_cmod;
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enum brw_conditional_mod new_cmod;
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new_cmod = brw_swap_cmod(inst->conditional_mod);
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if (new_cmod != ~0u) {
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@@ -57,7 +57,7 @@ void
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fs_visitor::emit_fp_minmax(const prog_instruction *fpi,
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fs_reg dst, fs_reg src0, fs_reg src1)
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{
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uint32_t conditionalmod;
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enum brw_conditional_mod conditionalmod;
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if (fpi->Opcode == OPCODE_MIN)
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conditionalmod = BRW_CONDITIONAL_L;
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else
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@@ -72,7 +72,7 @@ fs_visitor::emit_fp_minmax(const prog_instruction *fpi,
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}
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void
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fs_visitor::emit_fp_sop(uint32_t conditional_mod,
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fs_visitor::emit_fp_sop(enum brw_conditional_mod conditional_mod,
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const struct prog_instruction *fpi,
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fs_reg dst, fs_reg src0, fs_reg src1,
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fs_reg one)
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@@ -251,7 +251,7 @@ fs_visitor::emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
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}
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void
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fs_visitor::emit_minmax(uint32_t conditionalmod, const fs_reg &dst,
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fs_visitor::emit_minmax(enum brw_conditional_mod conditionalmod, const fs_reg &dst,
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const fs_reg &src0, const fs_reg &src1)
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{
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fs_inst *inst;
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@@ -2692,7 +2692,7 @@ fs_visitor::emit_color_write(int target, int index, int first_color_mrf)
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}
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}
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static int
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static enum brw_conditional_mod
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cond_for_alpha_func(GLenum func)
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{
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switch(func) {
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@@ -311,7 +311,7 @@ brw_type_for_base_type(const struct glsl_type *type)
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return BRW_REGISTER_TYPE_F;
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}
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uint32_t
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enum brw_conditional_mod
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brw_conditional_for_comparison(unsigned int op)
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{
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switch (op) {
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@@ -118,7 +118,7 @@ public:
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uint8_t mlen; /**< SEND message length */
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int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
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uint8_t target; /**< MRT target. */
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uint8_t conditional_mod; /**< BRW_CONDITIONAL_* */
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enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
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bool force_writemask_all:1;
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bool no_dd_clear:1;
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@@ -180,6 +180,6 @@ void annotation_finalize(struct annotation_info *annotation, unsigned offset);
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#endif /* __cplusplus */
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enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
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uint32_t brw_conditional_for_comparison(unsigned int op);
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enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
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uint32_t brw_math_function(enum opcode op);
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const char *brw_instruction_name(enum opcode op);
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@@ -441,8 +441,9 @@ public:
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vec4_instruction *ASR(const dst_reg &dst, const src_reg &src0,
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const src_reg &src1);
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vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
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uint32_t condition);
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vec4_instruction *IF(src_reg src0, src_reg src1, uint32_t condition);
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enum brw_conditional_mod condition);
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vec4_instruction *IF(src_reg src0, src_reg src1,
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enum brw_conditional_mod condition);
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vec4_instruction *IF(uint32_t predicate);
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vec4_instruction *PULL_CONSTANT_LOAD(const dst_reg &dst,
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const src_reg &index);
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@@ -479,14 +480,15 @@ public:
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/** Walks an exec_list of ir_instruction and sends it through this visitor. */
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void visit_instructions(const exec_list *list);
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void emit_vp_sop(uint32_t condmod, dst_reg dst,
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void emit_vp_sop(enum brw_conditional_mod condmod, dst_reg dst,
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src_reg src0, src_reg src1, src_reg one);
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void emit_bool_to_cond_code(ir_rvalue *ir, uint32_t *predicate);
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void emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1);
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void emit_if_gen6(ir_if *ir);
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void emit_minmax(uint32_t condmod, dst_reg dst, src_reg src0, src_reg src1);
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void emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
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src_reg src0, src_reg src1);
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void emit_lrp(const dst_reg &dst,
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const src_reg &x, const src_reg &y, const src_reg &a);
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@@ -162,7 +162,7 @@ try_constant_propagate(struct brw_context *brw, vec4_instruction *inst,
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inst->src[arg] = value;
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return true;
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} else if (arg == 0 && inst->src[1].file != IMM) {
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uint32_t new_cmod;
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enum brw_conditional_mod new_cmod;
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new_cmod = brw_swap_cmod(inst->conditional_mod);
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if (new_cmod != ~0u) {
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@@ -195,7 +195,8 @@ vec4_visitor::IF(uint32_t predicate)
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/** Gen6 IF with embedded comparison. */
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vec4_instruction *
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vec4_visitor::IF(src_reg src0, src_reg src1, uint32_t condition)
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vec4_visitor::IF(src_reg src0, src_reg src1,
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enum brw_conditional_mod condition)
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{
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assert(brw->gen == 6);
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@@ -217,7 +218,8 @@ vec4_visitor::IF(src_reg src0, src_reg src1, uint32_t condition)
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* the flag register with the packed 16 bits of the result.
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*/
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vec4_instruction *
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vec4_visitor::CMP(dst_reg dst, src_reg src0, src_reg src1, uint32_t condition)
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vec4_visitor::CMP(dst_reg dst, src_reg src0, src_reg src1,
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enum brw_conditional_mod condition)
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{
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vec4_instruction *inst;
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@@ -1185,7 +1187,7 @@ vec4_visitor::emit_bool_comparison(unsigned int op,
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}
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void
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vec4_visitor::emit_minmax(uint32_t conditionalmod, dst_reg dst,
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vec4_visitor::emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
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src_reg src0, src_reg src1)
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{
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vec4_instruction *inst;
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@@ -37,7 +37,7 @@ extern "C" {
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using namespace brw;
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void
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vec4_visitor::emit_vp_sop(uint32_t conditional_mod,
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vec4_visitor::emit_vp_sop(enum brw_conditional_mod conditional_mod,
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dst_reg dst, src_reg src0, src_reg src1,
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src_reg one)
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{
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@@ -28,6 +28,7 @@
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* and set various fields. This is the actual hardware format.
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*/
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#include "main/compiler.h"
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#include "brw_defines.h"
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#include "gen8_instruction.h"
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