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nir/algebraic: Optimize some open-coded extract_i8

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These were initially observed in Hogwarts Legacy while working on
something else entirely. Two compute shaders in that app are helped
for spills and fills. On Skylake, one of the shaders benefits from
this change, and the other is hurt pretty significantly.

About 40 vertex shaders in Shadow of the Tomb Raider were helped for
instructions.

v2: Use ~0xff instead of 0xffffff00 to ensure the patterns will work
properly with all bit sizes. Noticed by Georg.

v3: No, really, fix the various errors to ensure the patterns will work
properly with all bit sizes. Noticed by Georg.

No shader-db changes on any Intel platform.

fossil-db:

Lunar Lake, Meteor Lake, and DG2 had similar results. (Lunar Lake)
Totals:
Instrs: 210566294 -> 210561118 (-0.00%)
Cycle count: 31582309052 -> 31576352808 (-0.02%); split: -0.02%, +0.00%
Spill count: 519300 -> 519280 (-0.00%)
Fill count: 625181 -> 625161 (-0.00%)
Scratch Memory Size: 36289536 -> 36281344 (-0.02%)
Max live registers: 66068413 -> 66068161 (-0.00%)
Non SSA regs after NIR: 60230773 -> 60230775 (+0.00%)

Totals from 1662 (0.24% of 707082) affected shaders:
Instrs: 635064 -> 629888 (-0.82%)
Cycle count: 36549632 -> 30593388 (-16.30%); split: -16.43%, +0.14%
Spill count: 246 -> 226 (-8.13%)
Fill count: 280 -> 260 (-7.14%)
Scratch Memory Size: 16384 -> 8192 (-50.00%)
Max live registers: 178491 -> 178239 (-0.14%)
Non SSA regs after NIR: 169552 -> 169554 (+0.00%)

Tiger Lake
Totals:
Instrs: 238544730 -> 238539407 (-0.00%)
Cycle count: 23679446097 -> 23673238578 (-0.03%); split: -0.03%, +0.00%
Max live registers: 42494925 -> 42494799 (-0.00%)
Non SSA regs after NIR: 63639071 -> 63639074 (+0.00%)

Totals from 1662 (0.21% of 802704) affected shaders:
Instrs: 626604 -> 621281 (-0.85%)
Cycle count: 26444363 -> 20236844 (-23.47%); split: -23.50%, +0.02%
Max live registers: 95405 -> 95279 (-0.13%)
Non SSA regs after NIR: 181150 -> 181153 (+0.00%)

Ice Lake
Totals:
Instrs: 238855310 -> 238826534 (-0.01%)
Cycle count: 24952257277 -> 24944589398 (-0.03%); split: -0.03%, +0.00%
Spill count: 575510 -> 575117 (-0.07%)
Fill count: 713007 -> 708632 (-0.61%)
Max live registers: 42499556 -> 42499432 (-0.00%)
Non SSA regs after NIR: 64388747 -> 64388750 (+0.00%)

Totals from 1662 (0.21% of 805149) affected shaders:
Instrs: 926887 -> 898111 (-3.10%)
Cycle count: 67025583 -> 59357704 (-11.44%); split: -11.45%, +0.01%
Spill count: 5168 -> 4775 (-7.60%)
Fill count: 32883 -> 28508 (-13.30%)
Max live registers: 95614 -> 95490 (-0.13%)
Non SSA regs after NIR: 181150 -> 181153 (+0.00%)

Skylake
Totals:
Instrs: 161904416 -> 161895239 (-0.01%); split: -0.01%, +0.00%
Cycle count: 20098067714 -> 20090767583 (-0.04%); split: -0.04%, +0.00%
Spill count: 525546 -> 525789 (+0.05%); split: -0.04%, +0.09%
Fill count: 603369 -> 602276 (-0.18%); split: -0.28%, +0.10%
Max live registers: 33895714 -> 33895590 (-0.00%)
Non SSA regs after NIR: 57348729 -> 57348730 (+0.00%)

Totals from 1655 (0.25% of 653734) affected shaders:
Instrs: 769979 -> 760802 (-1.19%); split: -1.83%, +0.64%
Cycle count: 51365416 -> 44065285 (-14.21%); split: -14.22%, +0.01%
Spill count: 4186 -> 4429 (+5.81%); split: -4.90%, +10.70%
Fill count: 16356 -> 15263 (-6.68%); split: -10.50%, +3.82%
Max live registers: 95115 -> 94991 (-0.13%)
Non SSA regs after NIR: 180797 -> 180798 (+0.00%)

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34905>
This commit is contained in:
Ian Romanick
2025-04-21 15:11:43 -07:00
parent fca369f57a
commit 464955bbdd
1 changed files with 25 additions and 0 deletions
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src/compiler/nir/nir_opt_algebraic.py
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@@ -2020,6 +2020,31 @@ optimizations.extend([
(('extract_u8', ('iand', a, 0x00ff0000), 2), ('extract_u8', a, 2)),
(('extract_u8', ('iand', a, 0xff000000), 3), ('extract_u8', a, 3)),
(('ior', ('bcsel', ('ieq', ('iand', a, 0x00000080), 0), 0, ~0xff), ('extract_u8', a, 0)), ('extract_i8', a, 0)),
(('ior', ('bcsel', ('ieq', ('iand', a, 0x00008000), 0), 0, ~0xff), ('extract_u8', a, 1)), ('extract_i8', a, 1)),
(('ior', ('bcsel', ('ieq', ('iand', a, 0x00800000), 0), 0, ~0xff), ('extract_u8', a, 2)), ('extract_i8', a, 2)),
(('ior', ('bcsel', ('ige', 'a@32', 0), 0, ~0xff), ('extract_u8', a, 3)), ('extract_i8', a, 3)),
(('ior', ('bcsel', ('ine', ('iand', a, 0x00000080), 0), ~0xff, 0), ('extract_u8', a, 0)), ('extract_i8', a, 0)),
(('ior', ('bcsel', ('ine', ('iand', a, 0x00008000), 0), ~0xff, 0), ('extract_u8', a, 1)), ('extract_i8', a, 1)),
(('ior', ('bcsel', ('ine', ('iand', a, 0x00800000), 0), ~0xff, 0), ('extract_u8', a, 2)), ('extract_i8', a, 2)),
(('ior', ('bcsel', ('ilt', 'a@32', 0), ~0xff, 0), ('extract_u8', a, 3)), ('extract_i8', a, 3)),
(('extract_i8', ('ushr', a, 8), 0), ('extract_i8', a, 1)),
(('extract_i8', ('ushr', a, 8), 1), ('extract_i8', a, 2)),
(('extract_i8', ('ushr', a, 8), 2), ('extract_i8', a, 3)),
(('extract_u8', ('ushr', a, 8), 0), ('extract_u8', a, 1)),
(('extract_u8', ('ushr', a, 8), 1), ('extract_u8', a, 2)),
(('extract_u8', ('ushr', a, 8), 2), ('extract_u8', a, 3)),
(('extract_i8', ('extract_i16', a, 1), 0), ('extract_i8', a, 2)),
(('extract_i8', ('extract_i16', a, 1), 1), ('extract_i8', a, 3)),
(('extract_i8', ('extract_u16', a, 1), 0), ('extract_i8', a, 2)),
(('extract_i8', ('extract_u16', a, 1), 1), ('extract_i8', a, 3)),
(('extract_u8', ('extract_i16', a, 1), 0), ('extract_u8', a, 2)),
(('extract_u8', ('extract_i16', a, 1), 1), ('extract_u8', a, 3)),
(('extract_u8', ('extract_u16', a, 1), 0), ('extract_u8', a, 2)),
(('extract_u8', ('extract_u16', a, 1), 1), ('extract_u8', a, 3)),
(('iand', ('extract_u8', a, 0), '#b'), ('iand', a, ('iand', b, 0x00ff))),
(('iand', ('extract_u16', a, 0), '#b'), ('iand', a, ('iand', b, 0xffff))),