virgl: add initial images support (v2)
v2: add max image samples support Reviwed-by: Gert Wollny <gert.wollny@collabora.com>
This commit is contained in:
@@ -182,6 +182,20 @@ static void virgl_attach_res_shader_buffers(struct virgl_context *vctx,
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}
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}
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static void virgl_attach_res_shader_images(struct virgl_context *vctx,
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enum pipe_shader_type shader_type)
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{
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struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
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struct virgl_resource *res;
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unsigned i;
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for (i = 0; i < PIPE_MAX_SHADER_IMAGES; i++) {
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res = virgl_resource(vctx->images[shader_type][i]);
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if (res) {
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vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
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}
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}
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}
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/*
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* after flushing, the hw context still has a bunch of
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* resources bound, so we need to rebind those here.
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@@ -198,6 +212,7 @@ static void virgl_reemit_res(struct virgl_context *vctx)
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virgl_attach_res_sampler_views(vctx, shader_type);
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virgl_attach_res_uniform_buffers(vctx, shader_type);
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virgl_attach_res_shader_buffers(vctx, shader_type);
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virgl_attach_res_shader_images(vctx, shader_type);
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}
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virgl_attach_res_vertex_buffers(vctx);
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virgl_attach_res_so_targets(vctx);
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@@ -954,6 +969,34 @@ static void virgl_set_shader_buffers(struct pipe_context *ctx,
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virgl_encode_set_shader_buffers(vctx, shader, start_slot, count, buffers);
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}
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static void virgl_set_shader_images(struct pipe_context *ctx,
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enum pipe_shader_type shader,
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unsigned start_slot, unsigned count,
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const struct pipe_image_view *images)
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{
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struct virgl_context *vctx = virgl_context(ctx);
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struct virgl_screen *rs = virgl_screen(ctx->screen);
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for (unsigned i = 0; i < count; i++) {
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unsigned idx = start_slot + i;
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if (images) {
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if (images[i].resource) {
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pipe_resource_reference(&vctx->images[shader][idx], images[i].resource);
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continue;
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}
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}
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pipe_resource_reference(&vctx->images[shader][idx], NULL);
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}
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uint32_t max_shader_images = shader == PIPE_SHADER_FRAGMENT ?
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rs->caps.caps.v2.max_shader_image_frag_compute :
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rs->caps.caps.v2.max_shader_image_other_stages;
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if (!max_shader_images)
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return;
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virgl_encode_set_shader_images(vctx, shader, start_slot, count, images);
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}
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static void
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virgl_context_destroy( struct pipe_context *ctx )
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{
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@@ -1092,6 +1135,7 @@ struct pipe_context *virgl_context_create(struct pipe_screen *pscreen,
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vctx->base.blit = virgl_blit;
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vctx->base.set_shader_buffers = virgl_set_shader_buffers;
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vctx->base.set_shader_images = virgl_set_shader_images;
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virgl_init_context_resource_functions(&vctx->base);
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virgl_init_query_functions(vctx);
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virgl_init_so_functions(vctx);
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@@ -70,6 +70,7 @@ struct virgl_context {
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struct pipe_resource *ubos[PIPE_SHADER_TYPES][PIPE_MAX_CONSTANT_BUFFERS];
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struct pipe_resource *ssbos[PIPE_SHADER_TYPES][PIPE_MAX_SHADER_BUFFERS];
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struct pipe_resource *images[PIPE_SHADER_TYPES][PIPE_MAX_SHADER_BUFFERS];
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int num_transfers;
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int num_draws;
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struct list_head to_flush_bufs;
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@@ -943,3 +943,32 @@ int virgl_encode_set_shader_buffers(struct virgl_context *ctx,
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}
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return 0;
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}
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int virgl_encode_set_shader_images(struct virgl_context *ctx,
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enum pipe_shader_type shader,
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unsigned start_slot, unsigned count,
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const struct pipe_image_view *images)
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{
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int i;
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virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SHADER_IMAGES, 0, VIRGL_SET_SHADER_IMAGE_SIZE(count)));
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virgl_encoder_write_dword(ctx->cbuf, shader);
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virgl_encoder_write_dword(ctx->cbuf, start_slot);
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for (i = 0; i < count; i++) {
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if (images) {
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struct virgl_resource *res = virgl_resource(images[i].resource);
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virgl_encoder_write_dword(ctx->cbuf, images[i].format);
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virgl_encoder_write_dword(ctx->cbuf, images[i].access);
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virgl_encoder_write_dword(ctx->cbuf, images[i].u.buf.offset);
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virgl_encoder_write_dword(ctx->cbuf, images[i].u.buf.size);
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virgl_encoder_write_res(ctx, res);
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} else {
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virgl_encoder_write_dword(ctx->cbuf, 0);
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virgl_encoder_write_dword(ctx->cbuf, 0);
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virgl_encoder_write_dword(ctx->cbuf, 0);
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virgl_encoder_write_dword(ctx->cbuf, 0);
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virgl_encoder_write_dword(ctx->cbuf, 0);
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}
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}
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return 0;
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}
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@@ -263,4 +263,8 @@ int virgl_encode_set_shader_buffers(struct virgl_context *ctx,
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enum pipe_shader_type shader,
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unsigned start_slot, unsigned count,
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const struct pipe_shader_buffer *buffers);
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int virgl_encode_set_shader_images(struct virgl_context *ctx,
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enum pipe_shader_type shader,
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unsigned start_slot, unsigned count,
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const struct pipe_image_view *images);
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#endif
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@@ -307,6 +307,9 @@ struct virgl_caps_v2 {
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uint32_t max_vertex_attrib_stride;
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uint32_t max_shader_buffer_frag_compute;
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uint32_t max_shader_buffer_other_stages;
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uint32_t max_shader_image_frag_compute;
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uint32_t max_shader_image_other_stages;
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uint32_t max_image_samples;
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};
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union virgl_caps {
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@@ -87,6 +87,7 @@ enum virgl_context_cmd {
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VIRGL_CCMD_SET_TESS_STATE,
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VIRGL_CCMD_SET_MIN_SAMPLES,
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VIRGL_CCMD_SET_SHADER_BUFFERS,
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VIRGL_CCMD_SET_SHADER_IMAGES,
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};
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/*
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@@ -501,4 +502,15 @@ enum virgl_context_cmd {
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#define VIRGL_SET_SHADER_BUFFER_LENGTH(x) ((x) * VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE + 4)
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#define VIRGL_SET_SHADER_BUFFER_RES_HANDLE(x) ((x) * VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE + 5)
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/* set shader images */
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#define VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE 5
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#define VIRGL_SET_SHADER_IMAGE_SIZE(x) (VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE * (x)) + 2
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#define VIRGL_SET_SHADER_IMAGE_SHADER_TYPE 1
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#define VIRGL_SET_SHADER_IMAGE_START_SLOT 2
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#define VIRGL_SET_SHADER_IMAGE_FORMAT(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 3)
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#define VIRGL_SET_SHADER_IMAGE_ACCESS(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 4)
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#define VIRGL_SET_SHADER_IMAGE_LAYER_OFFSET(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 5)
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#define VIRGL_SET_SHADER_IMAGE_LEVEL_SIZE(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 6)
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#define VIRGL_SET_SHADER_IMAGE_RES_HANDLE(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 7)
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#endif
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@@ -375,6 +375,11 @@ virgl_get_shader_param(struct pipe_screen *screen,
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return vscreen->caps.caps.v2.max_shader_buffer_frag_compute;
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else
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return vscreen->caps.caps.v2.max_shader_buffer_other_stages;
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case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
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if (shader == PIPE_SHADER_FRAGMENT)
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return vscreen->caps.caps.v2.max_shader_image_frag_compute;
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else
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return vscreen->caps.caps.v2.max_shader_image_other_stages;
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case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
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case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
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case PIPE_SHADER_CAP_INT64_ATOMICS:
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@@ -494,6 +499,12 @@ virgl_is_format_supported( struct pipe_screen *screen,
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if (sample_count > 1) {
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if (!vscreen->caps.caps.v1.bset.texture_multisample)
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return FALSE;
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if (bind & PIPE_BIND_SHADER_IMAGE) {
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if (sample_count > vscreen->caps.caps.v2.max_image_samples)
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return FALSE;
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}
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if (sample_count > vscreen->caps.caps.v1.max_samples)
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return FALSE;
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}
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@@ -137,5 +137,6 @@ static inline void virgl_ws_fill_new_caps_defaults(struct virgl_drm_caps *caps)
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caps->caps.v2.shader_buffer_offset_alignment = 32;
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caps->caps.v2.capability_bits = 0;
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caps->caps.v2.max_vertex_attrib_stride = 0;
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caps->caps.v2.max_image_samples = 0;
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}
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#endif
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