vc4: Don't bother de-SSAing values that aren't part of phi webs.
We can just support them the same way we do load_const's SSA values.
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@@ -110,18 +110,32 @@ indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
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}
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static struct qreg *
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ntq_get_dest(struct vc4_compile *c, nir_dest dest)
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ntq_init_ssa_def(struct vc4_compile *c, nir_ssa_def *def)
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{
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assert(!dest.is_ssa);
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nir_register *reg = dest.reg.reg;
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struct hash_entry *entry = _mesa_hash_table_search(c->def_ht, reg);
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assert(reg->num_array_elems == 0);
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assert(dest.reg.base_offset == 0);
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struct qreg *qregs = entry->data;
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struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
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def->num_components);
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_mesa_hash_table_insert(c->def_ht, def, qregs);
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return qregs;
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}
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static struct qreg *
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ntq_get_dest(struct vc4_compile *c, nir_dest *dest)
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{
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if (dest->is_ssa) {
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struct qreg *qregs = ntq_init_ssa_def(c, &dest->ssa);
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for (int i = 0; i < dest->ssa.num_components; i++)
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qregs[i] = c->undef;
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return qregs;
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} else {
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nir_register *reg = dest->reg.reg;
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assert(dest->reg.base_offset == 0);
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assert(reg->num_array_elems == 0);
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struct hash_entry *entry =
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_mesa_hash_table_search(c->def_ht, reg);
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return entry->data;
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}
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}
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static struct qreg
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ntq_get_src(struct vc4_compile *c, nir_src src, int i)
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{
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@@ -433,7 +447,7 @@ ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
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texture_output[i]);
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}
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struct qreg *dest = ntq_get_dest(c, instr->dest);
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struct qreg *dest = ntq_get_dest(c, &instr->dest);
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for (int i = 0; i < 4; i++) {
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dest[i] = get_swizzled_channel(c, texture_output,
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c->key->tex[unit].swizzle[i]);
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@@ -800,7 +814,7 @@ ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
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for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
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srcs[i] = ntq_get_src(c, instr->src[i].src,
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instr->src[i].swizzle[0]);
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struct qreg *dest = ntq_get_dest(c, instr->dest.dest);
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struct qreg *dest = ntq_get_dest(c, &instr->dest.dest);
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for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
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dest[i] = srcs[i];
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return;
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@@ -814,7 +828,7 @@ ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
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/* Pick the channel to store the output in. */
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assert(!instr->dest.saturate);
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struct qreg *dest = ntq_get_dest(c, instr->dest.dest);
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struct qreg *dest = ntq_get_dest(c, &instr->dest.dest);
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assert(util_is_power_of_two(instr->dest.write_mask));
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dest += ffs(instr->dest.write_mask) - 1;
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@@ -1761,14 +1775,25 @@ ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
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static void
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ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
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{
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struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
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instr->def.num_components);
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struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
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for (int i = 0; i < instr->def.num_components; i++)
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qregs[i] = qir_uniform_ui(c, instr->value.u[i]);
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_mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
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}
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static void
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ntq_emit_ssa_undef(struct vc4_compile *c, nir_ssa_undef_instr *instr)
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{
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struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
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/* QIR needs there to be *some* value, so pick 0 (same as for
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* ntq_setup_registers().
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*/
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for (int i = 0; i < instr->def.num_components; i++)
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qregs[i] = qir_uniform_ui(c, 0);
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}
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static void
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ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
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{
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@@ -1776,7 +1801,7 @@ ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
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struct qreg *dest = NULL;
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if (info->has_dest) {
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dest = ntq_get_dest(c, instr->dest);
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dest = ntq_get_dest(c, &instr->dest);
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}
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switch (instr->intrinsic) {
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@@ -1844,6 +1869,10 @@ ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
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ntq_emit_load_const(c, nir_instr_as_load_const(instr));
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break;
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case nir_instr_type_ssa_undef:
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ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
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break;
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case nir_instr_type_tex:
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ntq_emit_tex(c, nir_instr_as_tex(instr));
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break;
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@@ -2008,7 +2037,7 @@ vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
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nir_remove_dead_variables(c->s);
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nir_convert_from_ssa(c->s, false);
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nir_convert_from_ssa(c->s, true);
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if (vc4_debug & VC4_DEBUG_SHADERDB) {
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fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
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