i965: Move must_use/has_separate_stencil fields to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

src/mesa/drivers/dri/i965/brw_context.h

@@ -877,6 +877,8 @@ struct brw_context
 
    bool emit_state_always;
    bool has_hiz;
+   bool has_separate_stencil;
+   bool must_use_separate_stencil;
    bool has_swizzling;
    bool has_surface_tile_offset;
    bool has_compr4;

src/mesa/drivers/dri/i965/brw_misc_state.c

@@ -629,7 +629,7 @@ brw_emit_depthbuffer(struct brw_context *brw)
        * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
        *     [DevGT+]: This field must be set to TRUE.
        */
-      assert(intel->has_separate_stencil);
+      assert(brw->has_separate_stencil);
 
       depth_surface_type = BRW_SURFACE_2D;
       width = stencil_irb->Base.Base.Width;

src/mesa/drivers/dri/i965/intel_context.c

@@ -495,8 +495,8 @@ intelInitContext(struct brw_context *brw,
       intel->is_g4x = true;
    }
 
-   intel->has_separate_stencil = brw->intelScreen->hw_has_separate_stencil;
-   intel->must_use_separate_stencil = brw->intelScreen->hw_must_use_separate_stencil;
+   brw->has_separate_stencil = brw->intelScreen->hw_has_separate_stencil;
+   brw->must_use_separate_stencil = brw->intelScreen->hw_must_use_separate_stencil;
    brw->has_hiz = intel->gen >= 6;
    intel->has_llc = brw->intelScreen->hw_has_llc;
    brw->has_swizzling = brw->intelScreen->hw_has_swizzling;
@@ -579,7 +579,7 @@ intelInitContext(struct brw_context *brw,
        brw->has_hiz = false;
        /* On gen6, you can only do separate stencil with HIZ. */
        if (intel->gen == 6)
-	  intel->has_separate_stencil = false;
+	  brw->has_separate_stencil = false;
    }
 
    if (driQueryOptionb(&brw->optionCache, "always_flush_batch")) {

src/mesa/drivers/dri/i965/intel_context.h

@@ -121,8 +121,6 @@ struct intel_context
    bool is_haswell;
    bool is_baytrail;
    bool is_g4x;
-   bool has_separate_stencil;
-   bool must_use_separate_stencil;
    bool has_llc;
 };
 

src/mesa/drivers/dri/i965/intel_fbo.c

@@ -214,10 +214,10 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer
    case GL_STENCIL_INDEX8_EXT:
    case GL_STENCIL_INDEX16_EXT:
       /* These aren't actual texture formats, so force them here. */
-      if (intel->has_separate_stencil) {
+      if (brw->has_separate_stencil) {
 	 rb->Format = MESA_FORMAT_S8;
       } else {
-	 assert(!intel->must_use_separate_stencil);
+	 assert(!brw->must_use_separate_stencil);
 	 rb->Format = MESA_FORMAT_S8_Z24;
       }
       break;
@@ -588,7 +588,7 @@ intel_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb)
                            stencilRb->mt_layer);
 	 }
       } else {
-	 if (!intel->has_separate_stencil) {
+	 if (!brw->has_separate_stencil) {
 	    fbo_incomplete(fb, "FBO incomplete: separate stencil "
                            "unsupported\n");
 	 }

src/mesa/drivers/dri/i965/intel_mipmap_tree.c

@@ -252,7 +252,6 @@ intel_miptree_create_layout(struct brw_context *brw,
                             bool for_bo,
                             GLuint num_samples)
 {
-   struct intel_context *intel = &brw->intel;
    struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1);
    if (!mt)
       return NULL;
@@ -368,9 +367,8 @@ intel_miptree_create_layout(struct brw_context *brw,
 
    if (!for_bo &&
        _mesa_get_format_base_format(format) == GL_DEPTH_STENCIL &&
-       (intel->must_use_separate_stencil ||
-	(intel->has_separate_stencil &&
-	 brw_is_hiz_depth_format(brw, format)))) {
+       (brw->must_use_separate_stencil ||
+	(brw->has_separate_stencil && brw_is_hiz_depth_format(brw, format)))) {
       mt->stencil_mt = intel_miptree_create(brw,
                                             mt->target,
                                             MESA_FORMAT_S8,