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intel/brw_asm: Add BranchCtrl support

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We emit it for gfx9, so the assembler should support it too.

Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31747>
This commit is contained in:
Sviatoslav Peleshko
2024-10-19 15:52:55 +03:00
committed by Marge Bot
parent aea7366613
commit 445df8d611
5 changed files with 24 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/intel/compiler/brw_asm_internal.h
View File

@@ -66,6 +66,7 @@ struct options {
unsigned access_mode:1;
unsigned compression_control:2;
unsigned thread_control:2;
unsigned branch_control:1;
unsigned no_dd_check:1; // Dependency control
unsigned no_dd_clear:1; // Dependency control
unsigned mask_control:1;

6
src/intel/compiler/brw_disasm.c
View File

@@ -58,8 +58,8 @@ brw_has_uip(const struct intel_device_info *devinfo, enum opcode opcode)
opcode == BRW_OPCODE_HALT;
}
static bool
has_branch_ctrl(const struct intel_device_info *devinfo, enum opcode opcode)
bool
brw_has_branch_ctrl(const struct intel_device_info *devinfo, enum opcode opcode)
{
switch (opcode) {
case BRW_OPCODE_IF:
@@ -2574,7 +2574,7 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa,
(devinfo->ver >= 12 ? brw_inst_atomic_control(devinfo, inst) :
brw_inst_thread_control(devinfo, inst)),
&space);
if (has_branch_ctrl(devinfo, opcode)) {
if (brw_has_branch_ctrl(devinfo, opcode)) {
err |= control(file, "branch ctrl", branch_ctrl,
brw_inst_branch_control(devinfo, inst), &space);
} else if (devinfo->ver < 20) {

1
src/intel/compiler/brw_eu.h
View File

@@ -157,6 +157,7 @@ void brw_init_codegen(const struct brw_isa_info *isa,
struct brw_codegen *p, void *mem_ctx);
bool brw_has_jip(const struct intel_device_info *devinfo, enum opcode opcode);
bool brw_has_uip(const struct intel_device_info *devinfo, enum opcode opcode);
bool brw_has_branch_ctrl(const struct intel_device_info *devinfo, enum opcode opcode);
const struct brw_shader_reloc *brw_get_shader_relocs(struct brw_codegen *p,
unsigned *num_relocs);
const unsigned *brw_get_program( struct brw_codegen *p, unsigned *sz );

17
src/intel/compiler/brw_gram.y
View File

@@ -298,7 +298,15 @@ i965_asm_set_instruction_options(struct brw_codegen *p,
}
brw_inst_set_debug_control(p->devinfo, brw_last_inst,
options.debug_control);
if (p->devinfo->ver < 20) {
if (brw_has_branch_ctrl(p->devinfo, brw_inst_opcode(p->isa, brw_last_inst))) {
if (options.acc_wr_control)
error(NULL, "Instruction does not support AccWrEnable\n");
brw_inst_set_branch_control(p->devinfo, brw_last_inst,
options.branch_control);
} else if (options.branch_control) {
error(NULL, "Instruction does not support BranchCtrl\n");
} else if (p->devinfo->ver < 20) {
brw_inst_set_acc_wr_control(p->devinfo, brw_last_inst,
options.acc_wr_control);
}
@@ -450,6 +458,9 @@ add_label(struct brw_codegen *p, const char* label_name, enum instr_label_type t
/* thread control */
%token ATOMIC SWITCH
/* branch control */
%token BRANCH_CTRL
/* quater control */
%token QTR_2Q QTR_3Q QTR_4Q QTR_2H QTR_2N QTR_3N QTR_4N QTR_5N
%token QTR_6N QTR_7N QTR_8N
@@ -579,6 +590,9 @@ add_instruction_option(struct options *options, struct instoption opt)
case ATOMIC:
options->thread_control |= BRW_THREAD_ATOMIC;
break;
case BRANCH_CTRL:
options->branch_control = true;
break;
case NODDCHK:
options->no_dd_check = true;
break;
@@ -2091,6 +2105,7 @@ instoption:
| EOT { $$.type = INSTOPTION_FLAG; $$.uint_value = EOT; }
| SWITCH { $$.type = INSTOPTION_FLAG; $$.uint_value = SWITCH; }
| ATOMIC { $$.type = INSTOPTION_FLAG; $$.uint_value = ATOMIC; }
| BRANCH_CTRL { $$.type = INSTOPTION_FLAG; $$.uint_value = BRANCH_CTRL; }
| CMPTCTRL { $$.type = INSTOPTION_FLAG; $$.uint_value = CMPTCTRL; }
| WECTRL { $$.type = INSTOPTION_FLAG; $$.uint_value = WECTRL; }
| QTR_2Q { $$.type = INSTOPTION_CHAN_OFFSET; $$.uint_value = 8; }

3
src/intel/compiler/brw_lex.l
View File

@@ -281,6 +281,9 @@ nomask { return MASK_DISABLE; }
atomic { return ATOMIC; }
switch { return SWITCH; }
/* Branch control */
BranchCtrl { return BRANCH_CTRL; }
/* Quarter Control */
1[HNQ] { }
"2Q" { return QTR_2Q; }