agx: Implement nir_op_pack_64_2x32_split
This maps to a collect where the dest size is 64 and the src size is 32. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19971>
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@@ -1088,6 +1088,12 @@ agx_emit_alu(agx_builder *b, nir_alu_instr *instr)
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return agx_convert_to(b, dst, agx_immediate(mode), s0, AGX_ROUND_RTE);
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}
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case nir_op_pack_64_2x32_split:
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{
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agx_index idx[] = { s0, s1 };
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return agx_emit_collect_to(b, dst, 2, idx);
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}
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/* Split a 64-bit word into 32-bit parts. Do not use null destinations to
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* let us CSE (and coalesce) the splits when both x and y are split.
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*/
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@@ -61,7 +61,7 @@ agx_write_registers(agx_instr *I, unsigned d)
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case AGX_OPCODE_LDCF:
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return 6;
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case AGX_OPCODE_COLLECT:
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return I->nr_srcs * size;
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return I->nr_srcs * agx_size_align_16(I->src[0].size);
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default:
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return size;
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}
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@@ -178,6 +178,10 @@ pick_regs(struct ra_ctx *rctx, agx_instr *I, unsigned d)
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if (base >= rctx->bound || (base + count) > rctx->bound)
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continue;
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/* Unaligned destinations can happen when dest size > src size */
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if (base % align)
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continue;
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if (!BITSET_TEST_RANGE(rctx->used_regs, base, base + count - 1))
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return base;
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}
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@@ -424,7 +428,7 @@ agx_ra(agx_context *ctx)
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if (ins->op == AGX_OPCODE_COLLECT) {
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assert(ins->dest[0].type == AGX_INDEX_REGISTER);
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unsigned base = ins->dest[0].value;
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unsigned width = agx_size_align_16(ins->dest[0].size);
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unsigned width = agx_size_align_16(ins->src[0].size);
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struct agx_copy *copies = alloca(sizeof(copies[0]) * ins->nr_srcs);
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unsigned n = 0;
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@@ -432,7 +436,7 @@ agx_ra(agx_context *ctx)
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/* Move the sources */
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agx_foreach_src(ins, i) {
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if (agx_is_null(ins->src[i])) continue;
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assert(ins->src[i].size == ins->dest[0].size);
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assert(ins->src[i].size == ins->src[0].size);
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copies[n++] = (struct agx_copy) {
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.dest = base + (i * width),
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