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intel/brw/xe3+: Relax SEND EOT register assignment restrictions.

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These restrictions have been removed from the hardware.  Make the code
enforcing and validating them conditional.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32758>
This commit is contained in:
Francisco Jerez
2024-09-18 14:26:04 -07:00
committed by Caio Oliveira
parent 8a5ec60442
commit 43d59c6186
2 changed files with 10 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/intel/compiler/brw_eu_validate.c
+9 -7
View File
@@ -327,13 +327,15 @@ send_restrictions(const struct brw_isa_info *isa,
inst->src[1].nr != BRW_ARF_NULL,
"src1 of split send must be a GRF or NULL");
ERROR_IF(brw_inst_eot(devinfo, inst->raw) &&
inst->src[0].nr < 112,
"send with EOT must use g112-g127");
ERROR_IF(brw_inst_eot(devinfo, inst->raw) &&
inst->src[1].file == FIXED_GRF &&
inst->src[1].nr < 112,
"send with EOT must use g112-g127");
if (devinfo->ver < 30) {
ERROR_IF(brw_inst_eot(devinfo, inst->raw) &&
inst->src[0].nr < 112,
"send with EOT must use g112-g127");
ERROR_IF(brw_inst_eot(devinfo, inst->raw) &&
inst->src[1].file == FIXED_GRF &&
inst->src[1].nr < 112,
"send with EOT must use g112-g127");
}
if (inst->src[0].file == FIXED_GRF && inst->src[1].file == FIXED_GRF) {
/* Assume minimums if we don't know */
src/intel/compiler/brw_fs_reg_allocate.cpp
+1 -1
View File
@@ -600,7 +600,7 @@ fs_reg_alloc::setup_inst_interference(const fs_inst *inst)
* We could just do "something high". Instead, we just pick the highest
* register that works.
*/
if (inst->eot) {
if (inst->eot && devinfo->ver < 30) {
const int vgrf = inst->opcode == SHADER_OPCODE_SEND ?
inst->src[2].nr : inst->src[0].nr;
const int size = DIV_ROUND_UP(fs->alloc.sizes[vgrf], reg_unit(devinfo));