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pan/mdg: Insert moves to load/store registers

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Ensures a valid schedule/regalloc is possible when vectors are used in
funny ways, as occurs in dEQP-GLES31 resulting in a scheduler hang (or
with prior patches, an RA failure).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
This commit is contained in:
Alyssa Rosenzweig
2021-06-09 13:19:41 -04:00
committed by Marge Bot
parent 5f37474403
commit 43cff98dff
1 changed files with 27 additions and 0 deletions
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src/panfrost/midgard/midgard_schedule.c
+27
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@@ -1497,9 +1497,36 @@ schedule_block(compiler_context *ctx, midgard_block *block)
free(liveness);
}
/* Insert moves to ensure we can register allocate load/store registers */
static void
mir_lower_ldst(compiler_context *ctx)
{
mir_foreach_instr_global_safe(ctx, I) {
if (I->type != TAG_LOAD_STORE_4) continue;
mir_foreach_src(I, s) {
if (s == 0) continue;
if (I->src[s] == ~0) continue;
if (I->swizzle[s][0] == 0) continue;
unsigned temp = make_compiler_temp(ctx);
midgard_instruction mov = v_mov(I->src[s], temp);
mov.mask = 0x1;
mov.dest_type = I->src_types[s];
for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c)
mov.swizzle[1][c] = I->swizzle[s][0];
mir_insert_instruction_before(ctx, I, mov);
I->src[s] = mov.dest;
I->swizzle[s][0] = 0;
}
}
}
void
midgard_schedule_program(compiler_context *ctx)
{
mir_lower_ldst(ctx);
midgard_promote_uniforms(ctx);
/* Must be lowered right before scheduling */