brw: Add an assertion that writemasks can be fully ignored

I noticed that our backend was completely ignoring writemasks, despite
them appearing on many of the intrinsics we're implementing.

Rhys Perry pointed out that nir_lower_mem_access_bitsizes is removing
all non-trivial writemasking today, so ssbo/global/shared/scratch/etc.
stores should only ever see all components enabled.  Which means what
we're doing is legitimate, if non-obvious.  Add an assert to make it
obvious.

Thanks a lot to Rhys for helping me rediscover what made this work.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38343>

src/intel/compiler/brw/brw_from_nir.cpp

@@ -7003,6 +7003,14 @@ brw_from_nir_emit_memory_access(nir_to_brw_state &ntb,
    const intel_device_info *devinfo = ntb.devinfo;
    brw_shader &s = ntb.s;
 
+   /* nir_lower_mem_access_bit_sizes should be eliminating non-trivial
+    * writemasks for us, and we fully ignore them here.  Assert that if
+    * they're present, the masks are trivial (all components written).
+    */
+   assert(!nir_intrinsic_has_write_mask(instr) ||
+          nir_intrinsic_write_mask(instr) ==
+          nir_component_mask(instr->num_components));
+
    brw_reg srcs[MEMORY_LOGICAL_NUM_SRCS];
 
    /* Start with some default values for most cases */