freedreno: resync generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
Rob Clark
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32814 bytes, from 2013-11-30 15:07:33)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 10925 bytes, from 2013-12-20 21:06:09)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 54008 bytes, from 2013-12-20 22:49:44)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32840 bytes, from 2014-01-05 14:44:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2014-01-05 14:44:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 12362 bytes, from 2014-01-07 14:47:36)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 54368 bytes, from 2014-01-05 14:44:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47)
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Copyright (C) 2013 by the following authors:
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Copyright (C) 2013-2014 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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Permission is hereby granted, free of charge, to any person obtaining
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||||
@@ -890,6 +890,39 @@ static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val)
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#define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9
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#define REG_A2XX_VGT_DRAW_INITIATOR 0x000021fc
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#define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f
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#define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0
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static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
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{
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return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK;
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}
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#define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0
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#define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6
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static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
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{
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return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK;
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}
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#define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600
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#define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9
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static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
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{
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return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK;
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}
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#define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800
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#define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11
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static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val)
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{
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return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK;
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}
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#define A2XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000
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#define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000
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#define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000
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#define A2XX_VGT_DRAW_INITIATOR_NUM_INDICES__MASK 0xffff0000
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#define A2XX_VGT_DRAW_INITIATOR_NUM_INDICES__SHIFT 16
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static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INDICES(uint32_t val)
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{
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return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INDICES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INDICES__MASK;
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}
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#define REG_A2XX_VGT_IMMED_DATA 0x000021fd
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@@ -28,6 +28,7 @@
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#include "util/u_math.h"
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#include "adreno_common.xml.h"
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#include "adreno_pm4.xml.h"
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#include "a2xx.xml.h"
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@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32814 bytes, from 2013-11-30 15:07:33)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 10925 bytes, from 2013-12-20 21:06:09)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 54008 bytes, from 2013-12-20 22:49:44)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32840 bytes, from 2014-01-05 14:44:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2014-01-05 14:44:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 12362 bytes, from 2014-01-07 14:47:36)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 54368 bytes, from 2014-01-05 14:44:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47)
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Copyright (C) 2013 by the following authors:
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Copyright (C) 2013-2014 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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Permission is hereby granted, free of charge, to any person obtaining
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||||
@@ -1179,6 +1179,10 @@ static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val)
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#define REG_A3XX_RB_Z_CLAMP_MAX 0x00002115
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#define REG_A3XX_VGT_BIN_BASE 0x000021e1
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#define REG_A3XX_VGT_BIN_SIZE 0x000021e2
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#define REG_A3XX_PC_VSTREAM_CONTROL 0x000021e4
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#define A3XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000
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#define A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16
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@@ -1534,11 +1538,11 @@ static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val)
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{
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return ((val) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK;
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}
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#define A3XX_SP_SP_CTRL_REG_LOMODE__MASK 0x00c00000
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#define A3XX_SP_SP_CTRL_REG_LOMODE__SHIFT 22
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static inline uint32_t A3XX_SP_SP_CTRL_REG_LOMODE(uint32_t val)
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#define A3XX_SP_SP_CTRL_REG_L0MODE__MASK 0x00c00000
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#define A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT 22
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static inline uint32_t A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val)
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{
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return ((val) << A3XX_SP_SP_CTRL_REG_LOMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_LOMODE__MASK;
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return ((val) << A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT) & A3XX_SP_SP_CTRL_REG_L0MODE__MASK;
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}
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#define REG_A3XX_SP_VS_CTRL_REG0 0x000022c4
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@@ -2131,6 +2135,39 @@ static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_op
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#define REG_A3XX_VGT_EVENT_INITIATOR 0x000021f9
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#define REG_A3XX_VGT_DRAW_INITIATOR 0x000021fc
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#define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f
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#define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0
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static inline uint32_t A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
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{
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return ((val) << A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK;
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}
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#define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0
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#define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6
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static inline uint32_t A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
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{
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return ((val) << A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK;
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}
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#define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600
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#define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9
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static inline uint32_t A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
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{
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return ((val) << A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK;
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}
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#define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800
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#define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11
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static inline uint32_t A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val)
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{
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return ((val) << A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK;
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}
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#define A3XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000
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#define A3XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000
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#define A3XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000
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#define A3XX_VGT_DRAW_INITIATOR_NUM_INDICES__MASK 0xffff0000
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#define A3XX_VGT_DRAW_INITIATOR_NUM_INDICES__SHIFT 16
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static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INDICES(uint32_t val)
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{
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return ((val) << A3XX_VGT_DRAW_INITIATOR_NUM_INDICES__SHIFT) & A3XX_VGT_DRAW_INITIATOR_NUM_INDICES__MASK;
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}
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#define REG_A3XX_VGT_IMMED_DATA 0x000021fd
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@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32814 bytes, from 2013-11-30 15:07:33)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 10925 bytes, from 2013-12-20 21:06:09)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 54008 bytes, from 2013-12-20 22:49:44)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32840 bytes, from 2014-01-05 14:44:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2014-01-05 14:44:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 12362 bytes, from 2014-01-07 14:47:36)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 54368 bytes, from 2014-01-05 14:44:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47)
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Copyright (C) 2013 by the following authors:
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||||
Copyright (C) 2013-2014 by the following authors:
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||||
- Rob Clark <robdclark@gmail.com> (robclark)
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Permission is hereby granted, free of charge, to any person obtaining
|
||||
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||||
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
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||||
The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32814 bytes, from 2013-11-30 15:07:33)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 10925 bytes, from 2013-12-20 21:06:09)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 54008 bytes, from 2013-12-20 22:49:44)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32840 bytes, from 2014-01-05 14:44:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2014-01-05 14:44:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 12362 bytes, from 2014-01-07 14:47:36)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 54368 bytes, from 2014-01-05 14:44:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47)
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Copyright (C) 2013 by the following authors:
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Copyright (C) 2013-2014 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
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Permission is hereby granted, free of charge, to any person obtaining
|
||||
@@ -105,6 +105,7 @@ enum pc_di_index_size {
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enum pc_di_vis_cull_mode {
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IGNORE_VISIBILITY = 0,
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USE_VISIBILITY = 1,
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};
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enum adreno_pm4_packet_type {
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@@ -232,6 +233,124 @@ static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
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return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
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}
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#define REG_CP_DRAW_INDX_0 0x00000000
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#define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
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#define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
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static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
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{
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return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
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}
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#define REG_CP_DRAW_INDX_1 0x00000001
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#define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f
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#define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0
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static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
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{
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return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
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}
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#define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0
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#define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6
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static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
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{
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return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
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}
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#define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600
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#define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9
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static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
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{
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return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
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||||
}
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#define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800
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#define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11
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static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
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{
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return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
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}
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#define CP_DRAW_INDX_1_NOT_EOP 0x00001000
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#define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000
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||||
#define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
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||||
#define CP_DRAW_INDX_1_NUM_INDICES__MASK 0xffff0000
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||||
#define CP_DRAW_INDX_1_NUM_INDICES__SHIFT 16
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static inline uint32_t CP_DRAW_INDX_1_NUM_INDICES(uint32_t val)
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||||
{
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return ((val) << CP_DRAW_INDX_1_NUM_INDICES__SHIFT) & CP_DRAW_INDX_1_NUM_INDICES__MASK;
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||||
}
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||||
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||||
#define REG_CP_DRAW_INDX_2 0x00000002
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||||
#define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff
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||||
#define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0
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||||
static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
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||||
{
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return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
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||||
}
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||||
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||||
#define REG_CP_DRAW_INDX_2 0x00000002
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||||
#define CP_DRAW_INDX_2_INDX_BASE__MASK 0xffffffff
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||||
#define CP_DRAW_INDX_2_INDX_BASE__SHIFT 0
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||||
static inline uint32_t CP_DRAW_INDX_2_INDX_BASE(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_2_INDX_BASE__SHIFT) & CP_DRAW_INDX_2_INDX_BASE__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_DRAW_INDX_2 0x00000002
|
||||
#define CP_DRAW_INDX_2_INDX_SIZE__MASK 0xffffffff
|
||||
#define CP_DRAW_INDX_2_INDX_SIZE__SHIFT 0
|
||||
static inline uint32_t CP_DRAW_INDX_2_INDX_SIZE(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_2_INDX_SIZE__SHIFT) & CP_DRAW_INDX_2_INDX_SIZE__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_DRAW_INDX_2_0 0x00000000
|
||||
#define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff
|
||||
#define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0
|
||||
static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_DRAW_INDX_2_1 0x00000001
|
||||
#define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f
|
||||
#define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0
|
||||
static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
|
||||
}
|
||||
#define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0
|
||||
#define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6
|
||||
static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
|
||||
}
|
||||
#define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600
|
||||
#define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9
|
||||
static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
|
||||
}
|
||||
#define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800
|
||||
#define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11
|
||||
static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
|
||||
}
|
||||
#define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000
|
||||
#define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000
|
||||
#define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
|
||||
#define CP_DRAW_INDX_2_1_NUM_INDICES__MASK 0xffff0000
|
||||
#define CP_DRAW_INDX_2_1_NUM_INDICES__SHIFT 16
|
||||
static inline uint32_t CP_DRAW_INDX_2_1_NUM_INDICES(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_2_1_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INDICES__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_DRAW_INDX_2_2 0x00000002
|
||||
#define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff
|
||||
#define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0
|
||||
static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_BIN_0 0x00000000
|
||||
|
||||
#define REG_CP_SET_BIN_1 0x00000001
|
||||
|
||||
Reference in New Issue
Block a user