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radeonsi/vcn: Deduplicate header encoding functions

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There is no need to separate these by VCN version.
For VCN < 3.0 transform skip must be disabled and for VCN < 2.0
SAO must be disabled.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30672>
This commit is contained in:
David Rosca
2024-08-13 13:52:46 +02:00
parent 32c6a61e2b
commit 40d01175be
5 changed files with 56 additions and 699 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/radeonsi/radeon_vcn_enc.c
+8 -2
View File
@@ -728,6 +728,8 @@ static void radeon_vcn_enc_hevc_get_metadata(struct radeon_encoder *enc,
static void radeon_vcn_enc_hevc_get_param(struct radeon_encoder *enc,
struct pipe_h265_enc_picture_desc *pic)
{
struct si_screen *sscreen = (struct si_screen *)enc->screen;
enc->enc_pic.picture_type = pic->picture_type;
enc->enc_pic.frame_num = pic->frame_num;
radeon_vcn_enc_quality_modes(enc, &pic->quality_modes);
@@ -773,8 +775,12 @@ static void radeon_vcn_enc_hevc_get_param(struct radeon_encoder *enc,
enc->enc_pic.bit_depth_chroma_minus8 = pic->seq.bit_depth_chroma_minus8;
enc->enc_pic.nal_unit_type = pic->pic.nal_unit_type;
enc->enc_pic.max_num_merge_cand = pic->slice.max_num_merge_cand;
enc->enc_pic.sample_adaptive_offset_enabled_flag =
pic->seq.sample_adaptive_offset_enabled_flag;
if (sscreen->info.vcn_ip_version >= VCN_2_0_0) {
enc->enc_pic.sample_adaptive_offset_enabled_flag =
pic->seq.sample_adaptive_offset_enabled_flag;
}
if (sscreen->info.vcn_ip_version >= VCN_3_0_0)
enc->enc_pic.transform_skip_enabled = true;
enc->enc_pic.pcm_enabled_flag = pic->seq.pcm_enabled_flag;
enc->enc_pic.sps_temporal_mvp_enabled_flag = pic->seq.sps_temporal_mvp_enabled_flag;
enc->enc_pic.header_flags.vps = pic->header_flags.vps;
src/gallium/drivers/radeonsi/radeon_vcn_enc.h
+1
View File
@@ -105,6 +105,7 @@ struct radeon_enc_pic {
bool need_sequence_header;
bool is_even_frame;
bool sample_adaptive_offset_enabled_flag;
bool transform_skip_enabled;
bool pcm_enabled_flag;
bool sps_temporal_mvp_enabled_flag;
bool use_rc_per_pic_ex;
src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c
+47 -15
View File
@@ -252,7 +252,7 @@ static void radeon_enc_nalu_sps(struct radeon_encoder *enc)
radeon_enc_byte_align(enc);
radeon_enc_set_emulation_prevention(enc, true);
radeon_enc_code_fixed_bits(enc, pic->spec_misc.profile_idc, 8);
radeon_enc_code_fixed_bits(enc, 0x44, 8); // hardcode to constrained baseline
radeon_enc_code_fixed_bits(enc, 0x0, 8); /* constraint_set_flags */
radeon_enc_code_fixed_bits(enc, pic->spec_misc.level_idc, 8);
radeon_enc_code_ue(enc, 0x0);
@@ -343,7 +343,7 @@ static void radeon_enc_nalu_sps(struct radeon_encoder *enc)
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_ue(enc, 16);
radeon_enc_code_ue(enc, 16);
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_ue(enc, pic->vui_info.max_num_reorder_frames);
radeon_enc_code_ue(enc, enc->base.max_references); /* max_dec_frame_buffering */
}
radeon_enc_code_fixed_bits(enc, 0x1, 1);
@@ -374,7 +374,12 @@ static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
radeon_enc_code_fixed_bits(enc, 0x0, 2);
radeon_enc_code_fixed_bits(enc, pic->general_tier_flag, 1);
radeon_enc_code_fixed_bits(enc, pic->general_profile_idc, 5);
radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
if (pic->general_profile_idc == 2)
radeon_enc_code_fixed_bits(enc, 0x20000000, 32);
else
radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
radeon_enc_code_fixed_bits(enc, 0x0, 16);
radeon_enc_code_fixed_bits(enc, pic->general_level_idc, 8);
@@ -441,7 +446,7 @@ static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
radeon_enc_code_fixed_bits(enc, 0, 1);
radeon_enc_code_fixed_bits(enc, pic->hevc_spec_misc.strong_intra_smoothing_enabled, 1);
/* VUI parameter present flag */
/* VUI parameters present flag */
radeon_enc_code_fixed_bits(enc, (pic->vui_info.vui_parameters_present_flag), 1);
if (pic->vui_info.vui_parameters_present_flag) {
/* aspect ratio present flag */
@@ -486,8 +491,7 @@ static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
}
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* bitstream restriction flag */
}
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* SPS extension present */
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* sps extension present flag */
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_byte_align(enc);
@@ -785,7 +789,7 @@ static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_se(enc, 0x0);
radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, enc->enc_pic.transform_skip_enabled_flag, 1);
if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE &&
enc->enc_pic.enc_qp_map.qp_map_type == RENCODE_QP_MAP_TYPE_NONE)
radeon_enc_code_fixed_bits(enc, 0x0, 1);
@@ -991,6 +995,9 @@ static void radeon_enc_slice_header(struct radeon_encoder *enc)
if (enc->enc_pic.pic_order_cnt_type == 0)
radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt % 32, 5);
if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)
radeon_enc_code_fixed_bits(enc, 0x1, 1); /* direct_spatial_mv_pred_flag */
/* ref_pic_list_modification() */
if (enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_IDR &&
enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_I) {
@@ -1005,6 +1012,10 @@ static void radeon_enc_slice_header(struct radeon_encoder *enc)
}
/* short-term reference */
else if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B) {
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* ref_pic_list_modification_flag_l0 */
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* ref_pic_list_modification_flag_l1 */
}
/* list_mod_diff_pic_minus1 != 0 */
else if (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 > 1) {
radeon_enc_code_fixed_bits(enc, 0x1, 1); /* ref_pic_list_modification_flag_l0 */
@@ -1148,6 +1159,17 @@ static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
}
}
if (enc->enc_pic.sample_adaptive_offset_enabled_flag) {
radeon_enc_flush_headers(enc);
instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
num_bits[inst_index] = enc->bits_output - bits_copied;
bits_copied = enc->bits_output;
inst_index++;
instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SAO_ENABLE;
inst_index++;
}
if ((enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P) ||
(enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)) {
radeon_enc_code_fixed_bits(enc, 0x0, 1);
@@ -1165,15 +1187,25 @@ static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
inst_index++;
if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
(!enc->enc_pic.hevc_deblock.deblocking_filter_disabled)) {
radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled,
1);
(!enc->enc_pic.hevc_deblock.deblocking_filter_disabled ||
enc->enc_pic.sample_adaptive_offset_enabled_flag)) {
if (enc->enc_pic.sample_adaptive_offset_enabled_flag) {
radeon_enc_flush_headers(enc);
instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
num_bits[inst_index] = enc->bits_output - bits_copied;
bits_copied = enc->bits_output;
inst_index++;
radeon_enc_flush_headers(enc);
instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
num_bits[inst_index] = enc->bits_output - bits_copied;
bits_copied = enc->bits_output;
inst_index++;
instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_LOOP_FILTER_ACROSS_SLICES_ENABLE;
inst_index++;
} else {
radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
radeon_enc_flush_headers(enc);
instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
num_bits[inst_index] = enc->bits_output - bits_copied;
bits_copied = enc->bits_output;
inst_index++;
}
}
instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
src/gallium/drivers/radeonsi/radeon_vcn_enc_2_0.c
-343
View File
@@ -86,141 +86,6 @@ static void radeon_enc_quality_params(struct radeon_encoder *enc)
RADEON_ENC_END();
}
static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
{
uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
unsigned int inst_index = 0;
unsigned int cdw_start = 0;
unsigned int cdw_filled = 0;
unsigned int bits_copied = 0;
RADEON_ENC_BEGIN(enc->cmd.slice_header);
radeon_enc_reset(enc);
radeon_enc_set_emulation_prevention(enc, false);
cdw_start = enc->cs.current.cdw;
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6);
radeon_enc_code_fixed_bits(enc, 0x0, 6);
radeon_enc_code_fixed_bits(enc, 0x1, 3);
radeon_enc_flush_headers(enc);
instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
num_bits[inst_index] = enc->bits_output - bits_copied;
bits_copied = enc->bits_output;
inst_index++;
instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE;
inst_index++;
if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23))
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_ue(enc, 0x0);
radeon_enc_flush_headers(enc);
instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
num_bits[inst_index] = enc->bits_output - bits_copied;
bits_copied = enc->bits_output;
inst_index++;
instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT;
inst_index++;
instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END;
inst_index++;
switch (enc->enc_pic.picture_type) {
case PIPE_H2645_ENC_PICTURE_TYPE_I:
case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
radeon_enc_code_ue(enc, 0x2);
break;
case PIPE_H2645_ENC_PICTURE_TYPE_P:
case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
radeon_enc_code_ue(enc, 0x1);
break;
case PIPE_H2645_ENC_PICTURE_TYPE_B:
radeon_enc_code_ue(enc, 0x0);
break;
default:
radeon_enc_code_ue(enc, 0x1);
}
if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) {
radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt, enc->enc_pic.log2_max_poc);
if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P)
radeon_enc_code_fixed_bits(enc, 0x1, 1);
else {
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_ue(enc, 0x0);
}
}
if (enc->enc_pic.sample_adaptive_offset_enabled_flag) {
radeon_enc_flush_headers(enc);
instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
num_bits[inst_index] = enc->bits_output - bits_copied;
bits_copied = enc->bits_output;
inst_index++;
instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SAO_ENABLE;
inst_index++;
}
if ((enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P) ||
(enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)) {
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
radeon_enc_code_ue(enc, 5 - enc->enc_pic.max_num_merge_cand);
}
radeon_enc_flush_headers(enc);
instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
num_bits[inst_index] = enc->bits_output - bits_copied;
bits_copied = enc->bits_output;
inst_index++;
instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA;
inst_index++;
if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
(!enc->enc_pic.hevc_deblock.deblocking_filter_disabled ||
enc->enc_pic.sample_adaptive_offset_enabled_flag)) {
if (enc->enc_pic.sample_adaptive_offset_enabled_flag) {
radeon_enc_flush_headers(enc);
instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
num_bits[inst_index] = enc->bits_output - bits_copied;
bits_copied = enc->bits_output;
inst_index++;
instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_LOOP_FILTER_ACROSS_SLICES_ENABLE;
inst_index++;
}
else
radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
}
radeon_enc_flush_headers(enc);
instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
num_bits[inst_index] = enc->bits_output - bits_copied;
bits_copied = enc->bits_output;
inst_index++;
instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
cdw_filled = enc->cs.current.cdw - cdw_start;
for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++)
RADEON_ENC_CS(0x00000000);
for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
RADEON_ENC_CS(instruction[j]);
RADEON_ENC_CS(num_bits[j]);
}
RADEON_ENC_END();
}
static void radeon_enc_loop_filter_hevc(struct radeon_encoder *enc)
{
RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_hevc);
@@ -234,211 +99,6 @@ static void radeon_enc_loop_filter_hevc(struct radeon_encoder *enc)
RADEON_ENC_END();
}
static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
{
struct radeon_enc_pic *pic = &enc->enc_pic;
RADEON_ENC_BEGIN(enc->cmd.nalu);
RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
int i;
radeon_enc_reset(enc);
radeon_enc_set_emulation_prevention(enc, false);
radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
radeon_enc_code_fixed_bits(enc, 0x4201, 16);
radeon_enc_byte_align(enc);
radeon_enc_set_emulation_prevention(enc, true);
radeon_enc_code_fixed_bits(enc, 0x0, 4);
radeon_enc_code_fixed_bits(enc, pic->layer_ctrl.max_num_temporal_layers - 1, 3);
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 2);
radeon_enc_code_fixed_bits(enc, pic->general_tier_flag, 1);
radeon_enc_code_fixed_bits(enc, pic->general_profile_idc, 5);
if (pic->general_profile_idc == 2)
radeon_enc_code_fixed_bits(enc, 0x20000000, 32);
else
radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
radeon_enc_code_fixed_bits(enc, 0x0, 16);
radeon_enc_code_fixed_bits(enc, pic->general_level_idc, 8);
for (i = 0; i < (pic->layer_ctrl.max_num_temporal_layers - 1); i++)
radeon_enc_code_fixed_bits(enc, 0x0, 2);
if ((pic->layer_ctrl.max_num_temporal_layers - 1) > 0) {
for (i = (pic->layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
radeon_enc_code_fixed_bits(enc, 0x0, 2);
}
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_ue(enc, pic->chroma_format_idc);
radeon_enc_code_ue(enc, pic->session_init.aligned_picture_width);
radeon_enc_code_ue(enc, pic->session_init.aligned_picture_height);
if ((pic->crop_left != 0) || (pic->crop_right != 0) ||
(pic->crop_top != 0) || (pic->crop_bottom != 0)) {
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_code_ue(enc, pic->crop_left);
radeon_enc_code_ue(enc, pic->crop_right);
radeon_enc_code_ue(enc, pic->crop_top);
radeon_enc_code_ue(enc, pic->crop_bottom);
} else if (pic->session_init.padding_width != 0 ||
pic->session_init.padding_height != 0) {
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_code_ue(enc, 0);
radeon_enc_code_ue(enc, pic->session_init.padding_width / 2);
radeon_enc_code_ue(enc, 0);
radeon_enc_code_ue(enc, pic->session_init.padding_height / 2);
} else
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_ue(enc, pic->bit_depth_luma_minus8);
radeon_enc_code_ue(enc, pic->bit_depth_chroma_minus8);
radeon_enc_code_ue(enc, pic->log2_max_poc - 4);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_ue(enc, 1);
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_ue(enc, pic->hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
// Only support CTBSize 64
radeon_enc_code_ue(enc,
6 - (pic->hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
radeon_enc_code_ue(enc, pic->log2_min_transform_block_size_minus2);
radeon_enc_code_ue(enc, pic->log2_diff_max_min_transform_block_size);
radeon_enc_code_ue(enc, pic->max_transform_hierarchy_depth_inter);
radeon_enc_code_ue(enc, pic->max_transform_hierarchy_depth_intra);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, !pic->hevc_spec_misc.amp_disabled, 1);
radeon_enc_code_fixed_bits(enc, pic->sample_adaptive_offset_enabled_flag, 1);
radeon_enc_code_fixed_bits(enc, pic->pcm_enabled_flag, 1);
radeon_enc_code_ue(enc, 1);
radeon_enc_code_ue(enc, 1);
radeon_enc_code_ue(enc, 0);
radeon_enc_code_ue(enc, 0);
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, 0, 1);
radeon_enc_code_fixed_bits(enc, pic->hevc_spec_misc.strong_intra_smoothing_enabled, 1);
/* VUI parameters present flag */
radeon_enc_code_fixed_bits(enc, (pic->vui_info.vui_parameters_present_flag), 1);
if (pic->vui_info.vui_parameters_present_flag) {
/* aspect ratio present flag */
radeon_enc_code_fixed_bits(enc, (pic->vui_info.flags.aspect_ratio_info_present_flag), 1);
if (pic->vui_info.flags.aspect_ratio_info_present_flag) {
radeon_enc_code_fixed_bits(enc, (pic->vui_info.aspect_ratio_idc), 8);
if (pic->vui_info.aspect_ratio_idc == PIPE_H2645_EXTENDED_SAR) {
radeon_enc_code_fixed_bits(enc, (pic->vui_info.sar_width), 16);
radeon_enc_code_fixed_bits(enc, (pic->vui_info.sar_height), 16);
}
}
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* overscan info present flag */
/* video signal type present flag */
radeon_enc_code_fixed_bits(enc, pic->vui_info.flags.video_signal_type_present_flag, 1);
if (pic->vui_info.flags.video_signal_type_present_flag) {
radeon_enc_code_fixed_bits(enc, pic->vui_info.video_format, 3);
radeon_enc_code_fixed_bits(enc, pic->vui_info.video_full_range_flag, 1);
radeon_enc_code_fixed_bits(enc, pic->vui_info.flags.colour_description_present_flag, 1);
if (pic->vui_info.flags.colour_description_present_flag) {
radeon_enc_code_fixed_bits(enc, pic->vui_info.colour_primaries, 8);
radeon_enc_code_fixed_bits(enc, pic->vui_info.transfer_characteristics, 8);
radeon_enc_code_fixed_bits(enc, pic->vui_info.matrix_coefficients, 8);
}
}
/* chroma loc info present flag */
radeon_enc_code_fixed_bits(enc, pic->vui_info.flags.chroma_loc_info_present_flag, 1);
if (pic->vui_info.flags.chroma_loc_info_present_flag) {
radeon_enc_code_ue(enc, pic->vui_info.chroma_sample_loc_type_top_field);
radeon_enc_code_ue(enc, pic->vui_info.chroma_sample_loc_type_bottom_field);
}
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* neutral chroma indication flag */
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* field seq flag */
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* frame field info present flag */
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* default display windows flag */
/* vui timing info present flag */
radeon_enc_code_fixed_bits(enc, (pic->vui_info.flags.timing_info_present_flag), 1);
if (pic->vui_info.flags.timing_info_present_flag) {
radeon_enc_code_fixed_bits(enc, (pic->vui_info.num_units_in_tick), 32);
radeon_enc_code_fixed_bits(enc, (pic->vui_info.time_scale), 32);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
}
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* bitstream restriction flag */
}
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* sps extension present flag */
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_byte_align(enc);
radeon_enc_flush_headers(enc);
*size_in_bytes = (enc->bits_output + 7) / 8;
RADEON_ENC_END();
}
static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
{
RADEON_ENC_BEGIN(enc->cmd.nalu);
RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
radeon_enc_reset(enc);
radeon_enc_set_emulation_prevention(enc, false);
radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
radeon_enc_code_fixed_bits(enc, 0x4401, 16);
radeon_enc_byte_align(enc);
radeon_enc_set_emulation_prevention(enc, true);
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 4);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_se(enc, 0x0);
radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE &&
enc->enc_pic.enc_qp_map.qp_map_type == RENCODE_QP_MAP_TYPE_NONE)
radeon_enc_code_fixed_bits(enc, 0x0, 1);
else {
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_code_ue(enc, 0x0);
}
radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 2);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
}
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
radeon_enc_code_fixed_bits(enc, 0x0, 2);
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_byte_align(enc);
radeon_enc_flush_headers(enc);
*size_in_bytes = (enc->bits_output + 7) / 8;
RADEON_ENC_END();
}
static void radeon_enc_input_format(struct radeon_encoder *enc)
{
RADEON_ENC_BEGIN(enc->cmd.input_format);
@@ -560,9 +220,6 @@ void radeon_enc_2_0_init(struct radeon_encoder *enc)
if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
enc->deblocking_filter = radeon_enc_loop_filter_hevc;
enc->nalu_sps = radeon_enc_nalu_sps_hevc;
enc->nalu_pps = radeon_enc_nalu_pps_hevc;
enc->slice_header = radeon_enc_slice_header_hevc;
}
enc->cmd.session_info = RENCODE_IB_PARAM_SESSION_INFO;
src/gallium/drivers/radeonsi/radeon_vcn_enc_3_0.c
-339
View File
@@ -139,342 +139,6 @@ static void radeon_enc_rc_per_pic_ex(struct radeon_encoder *enc)
RADEON_ENC_END();
}
static void radeon_enc_nalu_sps(struct radeon_encoder *enc)
{
struct radeon_enc_pic *pic = &enc->enc_pic;
RADEON_ENC_BEGIN(enc->cmd.nalu);
RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
radeon_enc_reset(enc);
radeon_enc_set_emulation_prevention(enc, false);
radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
radeon_enc_code_fixed_bits(enc, 0x67, 8);
radeon_enc_byte_align(enc);
radeon_enc_set_emulation_prevention(enc, true);
radeon_enc_code_fixed_bits(enc, pic->spec_misc.profile_idc, 8);
radeon_enc_code_fixed_bits(enc, 0x0, 8); /* constraint_set_flags */
radeon_enc_code_fixed_bits(enc, pic->spec_misc.level_idc, 8);
radeon_enc_code_ue(enc, 0x0);
if (pic->spec_misc.profile_idc == 100 || pic->spec_misc.profile_idc == 110 ||
pic->spec_misc.profile_idc == 122 || pic->spec_misc.profile_idc == 244 ||
pic->spec_misc.profile_idc == 44 || pic->spec_misc.profile_idc == 83 ||
pic->spec_misc.profile_idc == 86 || pic->spec_misc.profile_idc == 118 ||
pic->spec_misc.profile_idc == 128 || pic->spec_misc.profile_idc == 138) {
radeon_enc_code_ue(enc, 0x1);
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_fixed_bits(enc, 0x0, 2);
}
radeon_enc_code_ue(enc, 1);
radeon_enc_code_ue(enc, pic->pic_order_cnt_type);
if (pic->pic_order_cnt_type == 0)
radeon_enc_code_ue(enc, 1);
radeon_enc_code_ue(enc, enc->base.max_references);
radeon_enc_code_fixed_bits(enc, pic->layer_ctrl.max_num_temporal_layers > 1 ? 0x1 : 0x0,
1);
radeon_enc_code_ue(enc, (pic->session_init.aligned_picture_width / 16 - 1));
radeon_enc_code_ue(enc, (pic->session_init.aligned_picture_height / 16 - 1));
bool progressive_only = true;
radeon_enc_code_fixed_bits(enc, progressive_only ? 0x1 : 0x0, 1);
if (!progressive_only)
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, 0x1, 1);
if ((pic->crop_left != 0) || (pic->crop_right != 0) ||
(pic->crop_top != 0) || (pic->crop_bottom != 0)) {
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_code_ue(enc, pic->crop_left);
radeon_enc_code_ue(enc, pic->crop_right);
radeon_enc_code_ue(enc, pic->crop_top);
radeon_enc_code_ue(enc, pic->crop_bottom);
} else
radeon_enc_code_fixed_bits(enc, 0x0, 1);
/* VUI present flag */
radeon_enc_code_fixed_bits(enc, pic->vui_info.vui_parameters_present_flag, 1);
if (pic->vui_info.vui_parameters_present_flag) {
/* aspect ratio present flag */
radeon_enc_code_fixed_bits(enc, (pic->vui_info.flags.aspect_ratio_info_present_flag), 1);
if (pic->vui_info.flags.aspect_ratio_info_present_flag) {
radeon_enc_code_fixed_bits(enc, (pic->vui_info.aspect_ratio_idc), 8);
if (pic->vui_info.aspect_ratio_idc == PIPE_H2645_EXTENDED_SAR) {
radeon_enc_code_fixed_bits(enc, (pic->vui_info.sar_width), 16);
radeon_enc_code_fixed_bits(enc, (pic->vui_info.sar_height), 16);
}
}
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* overscan info present flag */
/* video signal type present flag */
radeon_enc_code_fixed_bits(enc, pic->vui_info.flags.video_signal_type_present_flag, 1);
if (pic->vui_info.flags.video_signal_type_present_flag) {
radeon_enc_code_fixed_bits(enc, pic->vui_info.video_format, 3);
radeon_enc_code_fixed_bits(enc, pic->vui_info.video_full_range_flag, 1);
radeon_enc_code_fixed_bits(enc, pic->vui_info.flags.colour_description_present_flag, 1);
if (pic->vui_info.flags.colour_description_present_flag) {
radeon_enc_code_fixed_bits(enc, pic->vui_info.colour_primaries, 8);
radeon_enc_code_fixed_bits(enc, pic->vui_info.transfer_characteristics, 8);
radeon_enc_code_fixed_bits(enc, pic->vui_info.matrix_coefficients, 8);
}
}
/* chroma loc info present flag */
radeon_enc_code_fixed_bits(enc, pic->vui_info.flags.chroma_loc_info_present_flag, 1);
if (pic->vui_info.flags.chroma_loc_info_present_flag) {
radeon_enc_code_ue(enc, pic->vui_info.chroma_sample_loc_type_top_field);
radeon_enc_code_ue(enc, pic->vui_info.chroma_sample_loc_type_bottom_field);
}
/* timing info present flag */
radeon_enc_code_fixed_bits(enc, (pic->vui_info.flags.timing_info_present_flag), 1);
if (pic->vui_info.flags.timing_info_present_flag) {
radeon_enc_code_fixed_bits(enc, (pic->vui_info.num_units_in_tick), 32);
radeon_enc_code_fixed_bits(enc, (pic->vui_info.time_scale), 32);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
}
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* nal hrd parameters present flag */
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* vcl hrd parameters present flag */
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* pic_struct_present flag */
radeon_enc_code_fixed_bits(enc, 0x1, 1); /* bitstream_restriction_flag */
radeon_enc_code_fixed_bits(enc, 0x1, 1); /* motion_vectors_over_pic_boundaries_flag */
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_ue(enc, 16);
radeon_enc_code_ue(enc, 16);
radeon_enc_code_ue(enc, pic->vui_info.max_num_reorder_frames);
radeon_enc_code_ue(enc, enc->base.max_references); /* max_dec_frame_buffering */
}
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_byte_align(enc);
radeon_enc_flush_headers(enc);
*size_in_bytes = (enc->bits_output + 7) / 8;
RADEON_ENC_END();
}
static void radeon_enc_slice_header(struct radeon_encoder *enc)
{
uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
unsigned int inst_index = 0;
unsigned int cdw_start = 0;
unsigned int cdw_filled = 0;
unsigned int bits_copied = 0;
RADEON_ENC_BEGIN(enc->cmd.slice_header);
radeon_enc_reset(enc);
radeon_enc_set_emulation_prevention(enc, false);
cdw_start = enc->cs.current.cdw;
if (enc->enc_pic.is_idr)
radeon_enc_code_fixed_bits(enc, 0x65, 8);
else if (enc->enc_pic.not_referenced)
radeon_enc_code_fixed_bits(enc, 0x01, 8);
else
radeon_enc_code_fixed_bits(enc, 0x41, 8);
radeon_enc_flush_headers(enc);
instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
num_bits[inst_index] = enc->bits_output - bits_copied;
bits_copied = enc->bits_output;
inst_index++;
instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB;
inst_index++;
switch (enc->enc_pic.picture_type) {
case PIPE_H2645_ENC_PICTURE_TYPE_I:
case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
radeon_enc_code_fixed_bits(enc, 0x08, 7);
break;
case PIPE_H2645_ENC_PICTURE_TYPE_P:
case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
radeon_enc_code_fixed_bits(enc, 0x06, 5);
break;
case PIPE_H2645_ENC_PICTURE_TYPE_B:
radeon_enc_code_fixed_bits(enc, 0x07, 5);
break;
default:
radeon_enc_code_fixed_bits(enc, 0x08, 7);
}
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % 32, 5);
if (enc->enc_pic.h264_enc_params.input_picture_structure !=
RENCODE_H264_PICTURE_STRUCTURE_FRAME) {
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_code_fixed_bits(enc,
enc->enc_pic.h264_enc_params.input_picture_structure ==
RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD
? 1
: 0,
1);
}
if (enc->enc_pic.is_idr)
radeon_enc_code_ue(enc, enc->enc_pic.is_even_frame);
enc->enc_pic.is_even_frame = !enc->enc_pic.is_even_frame;
if (enc->enc_pic.pic_order_cnt_type == 0)
radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt % 32, 5);
if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)
radeon_enc_code_fixed_bits(enc, 0x1, 1); /* direct_spatial_mv_pred_flag */
/* ref_pic_list_modification() */
if (enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_IDR &&
enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_I) {
radeon_enc_code_fixed_bits(enc, 0x0, 1);
/* long-term reference */
if (enc->enc_pic.ref_idx_l0_is_ltr) {
radeon_enc_code_fixed_bits(enc, 0x1, 1); /* ref_pic_list_modification_flag_l0 */
radeon_enc_code_ue(enc, 0x2); /* modification_of_pic_nums_idc */
radeon_enc_code_ue(enc, enc->enc_pic.ref_idx_l0); /* long_term_pic_num */
radeon_enc_code_ue(enc, 0x3);
}
/* short-term reference */
else if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B) {
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* ref_pic_list_modification_flag_l0 */
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* ref_pic_list_modification_flag_l1 */
}
/* list_mod_diff_pic_minus1 != 0 */
else if (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 > 1) {
radeon_enc_code_fixed_bits(enc, 0x1, 1); /* ref_pic_list_modification_flag_l0 */
radeon_enc_code_ue(enc, 0x0); /* modification_of_pic_nums_idc */
/* abs_diff_pic_num_minus1 */
radeon_enc_code_ue(enc, (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 - 1));
radeon_enc_code_ue(enc, 0x3);
} else
radeon_enc_code_fixed_bits(enc, 0x0, 1);
}
if (enc->enc_pic.is_idr) {
radeon_enc_code_fixed_bits(enc, 0x0, 1);
if (enc->enc_pic.is_ltr)
radeon_enc_code_fixed_bits(enc, 0x1, 1); /* long_term_reference_flag */
else
radeon_enc_code_fixed_bits(enc, 0x0, 1);
} else if (!enc->enc_pic.not_referenced) {
if (enc->enc_pic.is_ltr) {
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_code_ue(enc, 0x4); /* memory_management_control_operation */
radeon_enc_code_ue(enc, enc->max_ltr_idx + 1); /* max_long_term_frame_idx_plus1 */
radeon_enc_code_ue(enc, 0x6); /*memory_management_control_operation */
radeon_enc_code_ue(enc, enc->enc_pic.ltr_idx); /* long_term_frame_idx */
radeon_enc_code_ue(enc, 0x0); /*memory_management_control_operation end*/
} else
radeon_enc_code_fixed_bits(enc, 0x0, 1);
}
if ((enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_IDR) &&
(enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_I) &&
(enc->enc_pic.spec_misc.cabac_enable))
radeon_enc_code_ue(enc, enc->enc_pic.spec_misc.cabac_init_idc);
radeon_enc_flush_headers(enc);
instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
num_bits[inst_index] = enc->bits_output - bits_copied;
bits_copied = enc->bits_output;
inst_index++;
instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA;
inst_index++;
if (enc->enc_pic.spec_misc.deblocking_filter_control_present_flag) {
radeon_enc_code_ue(enc, enc->enc_pic.h264_deblock.disable_deblocking_filter_idc);
if (!enc->enc_pic.h264_deblock.disable_deblocking_filter_idc) {
radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.beta_offset_div2);
}
}
radeon_enc_flush_headers(enc);
instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
num_bits[inst_index] = enc->bits_output - bits_copied;
bits_copied = enc->bits_output;
inst_index++;
instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
cdw_filled = enc->cs.current.cdw - cdw_start;
for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++)
RADEON_ENC_CS(0x00000000);
for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
RADEON_ENC_CS(instruction[j]);
RADEON_ENC_CS(num_bits[j]);
}
RADEON_ENC_END();
}
static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
{
uint32_t *size_in_bytes;
RADEON_ENC_BEGIN(enc->cmd.nalu);
RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
radeon_enc_reset(enc);
radeon_enc_set_emulation_prevention(enc, false);
radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
radeon_enc_code_fixed_bits(enc, 0x4401, 16);
radeon_enc_byte_align(enc);
radeon_enc_set_emulation_prevention(enc, true);
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 4);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_se(enc, 0x0);
radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
radeon_enc_code_fixed_bits(enc, 0x1, 1);
if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE &&
enc->enc_pic.enc_qp_map.qp_map_type == RENCODE_QP_MAP_TYPE_NONE)
radeon_enc_code_fixed_bits(enc, 0x0, 1);
else {
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_code_ue(enc, 0x0);
}
radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 2);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
}
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
radeon_enc_code_fixed_bits(enc, 0x0, 2);
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_byte_align(enc);
radeon_enc_flush_headers(enc);
*size_in_bytes = (enc->bits_output + 7) / 8;
RADEON_ENC_END();
}
static uint32_t radeon_enc_ref_swizzle_mode(struct radeon_encoder *enc)
{
/* return RENCODE_REC_SWIZZLE_MODE_LINEAR; for debugging purpose */
@@ -568,13 +232,10 @@ void radeon_enc_3_0_init(struct radeon_encoder *enc)
if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
enc->spec_misc = radeon_enc_spec_misc;
enc->encode_params_codec_spec = radeon_enc_encode_params_h264;
enc->nalu_sps = radeon_enc_nalu_sps;
enc->slice_header = radeon_enc_slice_header;
}
if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
enc->spec_misc = radeon_enc_spec_misc_hevc;
enc->nalu_pps = radeon_enc_nalu_pps_hevc;
}
enc->enc_pic.session_info.interface_version =