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[intel-gem] Chase domain flag renaming in the DRM.

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This is an API breakage only.
This commit is contained in:
Eric Anholt
2008-06-11 14:44:48 -07:00
parent 0227d91a9e
commit 407ce3da3c
14 changed files with 41 additions and 41 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/mesa/drivers/dri/i915/i830_vtbl.c
+3 -3
View File
@@ -490,14 +490,14 @@ i830_emit_state(struct intel_context *intel)
OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]);
OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]);
OUT_RELOC(state->draw_region->buffer,
DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
state->draw_region->draw_offset);
if (state->depth_region) {
OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR0]);
OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR1]);
OUT_RELOC(state->depth_region->buffer,
DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
state->depth_region->draw_offset);
}
@@ -524,7 +524,7 @@ i830_emit_state(struct intel_context *intel)
if (state->tex_buffer[i]) {
OUT_RELOC(state->tex_buffer[i],
DRM_GEM_DOMAIN_I915_SAMPLER, 0,
I915_GEM_DOMAIN_SAMPLER, 0,
state->tex_offset[i] | TM0S0_USE_FENCE);
}
else if (state == &i830->meta) {
src/mesa/drivers/dri/i915/i915_vtbl.c
+3 -3
View File
@@ -377,14 +377,14 @@ i915_emit_state(struct intel_context *intel)
OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
OUT_RELOC(state->draw_region->buffer,
DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
state->draw_region->draw_offset);
if (state->depth_region) {
OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
OUT_RELOC(state->depth_region->buffer,
DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
state->depth_region->draw_offset);
}
@@ -427,7 +427,7 @@ i915_emit_state(struct intel_context *intel)
if (state->tex_buffer[i]) {
OUT_RELOC(state->tex_buffer[i],
DRM_GEM_DOMAIN_I915_SAMPLER, 0,
I915_GEM_DOMAIN_SAMPLER, 0,
state->tex_offset[i]);
}
else if (state == &i915->meta) {
src/mesa/drivers/dri/i965/brw_cc.c
+1 -1
View File
@@ -257,7 +257,7 @@ cc_unit_create_from_key(struct brw_context *brw, struct brw_cc_unit_key *key)
/* Emit CC viewport relocation */
intel_bo_emit_reloc(bo,
DRM_GEM_DOMAIN_I915_INSTRUCTION,
I915_GEM_DOMAIN_INSTRUCTION,
0,
0,
offsetof(struct brw_cc_unit_state, cc4),
src/mesa/drivers/dri/i965/brw_clip_state.c
+1 -1
View File
@@ -120,7 +120,7 @@ clip_unit_create_from_key(struct brw_context *brw,
/* Emit clip program relocation */
assert(brw->clip.prog_bo);
intel_bo_emit_reloc(bo,
DRM_GEM_DOMAIN_I915_INSTRUCTION,
I915_GEM_DOMAIN_INSTRUCTION,
0,
clip.thread0.grf_reg_count << 1,
offsetof(struct brw_clip_unit_state, thread0),
src/mesa/drivers/dri/i965/brw_curbe.c
+1 -1
View File
@@ -351,7 +351,7 @@ static void emit_constant_buffer(struct brw_context *brw)
} else {
OUT_BATCH((CMD_CONST_BUFFER << 16) | (1 << 8) | (2 - 2));
OUT_RELOC(brw->curbe.curbe_bo,
DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
I915_GEM_DOMAIN_INSTRUCTION, 0,
(sz - 1) + brw->curbe.curbe_offset);
}
ADVANCE_BATCH();
src/mesa/drivers/dri/i965/brw_draw_upload.c
+3 -3
View File
@@ -467,7 +467,7 @@ void brw_emit_vertices( struct brw_context *brw,
BRW_VB0_ACCESS_VERTEXDATA |
(input->stride << BRW_VB0_PITCH_SHIFT));
OUT_RELOC(input->bo,
DRM_GEM_DOMAIN_I915_VERTEX, 0,
I915_GEM_DOMAIN_VERTEX, 0,
input->offset);
OUT_BATCH(max_index);
OUT_BATCH(0); /* Instance data step rate */
@@ -589,10 +589,10 @@ void brw_emit_indices(struct brw_context *brw,
BEGIN_BATCH(4, IGNORE_CLIPRECTS);
OUT_BATCH( ib.header.dword );
OUT_RELOC( bo,
DRM_GEM_DOMAIN_I915_VERTEX, 0,
I915_GEM_DOMAIN_VERTEX, 0,
offset);
OUT_RELOC( bo,
DRM_GEM_DOMAIN_I915_VERTEX, 0,
I915_GEM_DOMAIN_VERTEX, 0,
offset + ib_size);
OUT_BATCH( 0 );
ADVANCE_BATCH();
src/mesa/drivers/dri/i965/brw_gs_state.c
+1 -1
View File
@@ -107,7 +107,7 @@ gs_unit_create_from_key(struct brw_context *brw, struct brw_gs_unit_key *key)
if (key->prog_active) {
/* Emit GS program relocation */
intel_bo_emit_reloc(bo,
DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
I915_GEM_DOMAIN_INSTRUCTION, 0,
gs.thread0.grf_reg_count << 1,
offsetof(struct brw_gs_unit_state, thread0),
brw->gs.prog_bo);
src/mesa/drivers/dri/i965/brw_misc_state.c
+8 -8
View File
@@ -89,7 +89,7 @@ static void upload_binding_table_pointers(struct brw_context *brw)
OUT_BATCH(0); /* clip */
OUT_BATCH(0); /* sf */
OUT_RELOC(brw->wm.bind_bo,
DRM_GEM_DOMAIN_I915_SAMPLER, 0,
I915_GEM_DOMAIN_SAMPLER, 0,
0);
ADVANCE_BATCH();
}
@@ -116,18 +116,18 @@ static void upload_pipelined_state_pointers(struct brw_context *brw )
BEGIN_BATCH(7, IGNORE_CLIPRECTS);
OUT_BATCH(CMD_PIPELINED_STATE_POINTERS << 16 | (7 - 2));
OUT_RELOC(brw->vs.state_bo, DRM_GEM_DOMAIN_I915_INSTRUCTION, 0, 0);
OUT_RELOC(brw->vs.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
if (brw->gs.prog_active)
OUT_RELOC(brw->gs.state_bo, DRM_GEM_DOMAIN_I915_INSTRUCTION, 0, 1);
OUT_RELOC(brw->gs.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
else
OUT_BATCH(0);
if (!brw->metaops.active)
OUT_RELOC(brw->clip.state_bo, DRM_GEM_DOMAIN_I915_INSTRUCTION, 0, 1);
OUT_RELOC(brw->clip.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
else
OUT_BATCH(0);
OUT_RELOC(brw->sf.state_bo, DRM_GEM_DOMAIN_I915_INSTRUCTION, 0, 0);
OUT_RELOC(brw->wm.state_bo, DRM_GEM_DOMAIN_I915_INSTRUCTION, 0, 0);
OUT_RELOC(brw->cc.state_bo, DRM_GEM_DOMAIN_I915_INSTRUCTION, 0, 0);
OUT_RELOC(brw->sf.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
OUT_RELOC(brw->wm.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
OUT_RELOC(brw->cc.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
ADVANCE_BATCH();
brw->state.dirty.brw |= BRW_NEW_PSP;
@@ -235,7 +235,7 @@ static void emit_depthbuffer(struct brw_context *brw)
(region->tiled << 27) |
(BRW_SURFACE_2D << 29));
OUT_RELOC(region->buffer,
DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
((region->pitch - 1) << 6) |
src/mesa/drivers/dri/i965/brw_sf_state.c
+2 -2
View File
@@ -254,14 +254,14 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
/* Emit SF program relocation */
intel_bo_emit_reloc(bo,
DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
I915_GEM_DOMAIN_INSTRUCTION, 0,
sf.thread0.grf_reg_count << 1,
offsetof(struct brw_sf_unit_state, thread0),
brw->sf.prog_bo);
/* Emit SF viewport relocation */
intel_bo_emit_reloc(bo,
DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
I915_GEM_DOMAIN_INSTRUCTION, 0,
sf.sf5.front_winding | (sf.sf5.viewport_transform << 1),
offsetof(struct brw_sf_unit_state, sf5),
brw->sf.vp_bo);
src/mesa/drivers/dri/i965/brw_vs_state.c
+1 -1
View File
@@ -116,7 +116,7 @@ vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key)
/* Emit VS program relocation */
intel_bo_emit_reloc(bo,
DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
I915_GEM_DOMAIN_INSTRUCTION, 0,
vs.thread0.grf_reg_count << 1,
offsetof(struct brw_vs_unit_state, thread0),
brw->vs.prog_bo);
src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
+1 -1
View File
@@ -306,7 +306,7 @@ static int upload_wm_samplers( struct brw_context *brw )
ret |= dri_bufmgr_check_aperture_space(brw->wm.sdc_bo[i]);
intel_bo_emit_reloc(brw->wm.sampler_bo,
DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
I915_GEM_DOMAIN_INSTRUCTION, 0,
0,
i * sizeof(struct brw_sampler_state) +
offsetof(struct brw_sampler_state, ss2),
src/mesa/drivers/dri/i965/brw_wm_state.c
+2 -2
View File
@@ -200,7 +200,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
/* Emit WM program relocation */
intel_bo_emit_reloc(bo,
DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
I915_GEM_DOMAIN_INSTRUCTION, 0,
wm.thread0.grf_reg_count << 1,
offsetof(struct brw_wm_unit_state, thread0),
brw->wm.prog_bo);
@@ -217,7 +217,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
/* Emit sampler state relocation */
if (key->sampler_count != 0) {
intel_bo_emit_reloc(bo,
DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
I915_GEM_DOMAIN_INSTRUCTION, 0,
wm.wm4.stats_enable | (wm.wm4.sampler_count << 2),
offsetof(struct brw_wm_unit_state, wm4),
brw->wm.sampler_bo);
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+5 -5
View File
@@ -204,7 +204,7 @@ brw_create_texture_surface( struct brw_context *brw,
/* Emit relocation to surface contents */
intel_bo_emit_reloc(bo,
DRM_GEM_DOMAIN_I915_SAMPLER, 0,
I915_GEM_DOMAIN_SAMPLER, 0,
0,
offsetof(struct brw_surface_state, ss1),
key->bo);
@@ -342,9 +342,9 @@ brw_update_region_surface(struct brw_context *brw, struct intel_region *region,
* a more restrictive relocation to emit.
*/
intel_bo_emit_reloc(brw->wm.surf_bo[unit],
DRM_GEM_DOMAIN_I915_RENDER |
DRM_GEM_DOMAIN_I915_SAMPLER,
DRM_GEM_DOMAIN_I915_RENDER,
I915_GEM_DOMAIN_RENDER |
I915_GEM_DOMAIN_SAMPLER,
I915_GEM_DOMAIN_RENDER,
0,
offsetof(struct brw_surface_state, ss1),
region_bo);
@@ -392,7 +392,7 @@ brw_wm_get_binding_table(struct brw_context *brw)
for (i = 0; i < BRW_WM_MAX_SURF; i++) {
if (brw->wm.surf_bo[i] != NULL) {
intel_bo_emit_reloc(bind_bo,
DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
I915_GEM_DOMAIN_INSTRUCTION, 0,
0,
i * sizeof(GLuint),
brw->wm.surf_bo[i]);
src/mesa/drivers/dri/intel/intel_blit.c
+9 -9
View File
@@ -149,12 +149,12 @@ intelCopyBuffer(const __DRIdrawablePrivate * dPriv,
OUT_BATCH((box.y2 << 16) | box.x2);
OUT_RELOC(dst->buffer,
DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
OUT_BATCH((src_y << 16) | src_x);
OUT_BATCH(src_pitch);
OUT_RELOC(src->buffer,
DRM_GEM_DOMAIN_I915_RENDER, 0,
I915_GEM_DOMAIN_RENDER, 0,
0);
ADVANCE_BATCH();
}
@@ -225,7 +225,7 @@ intelEmitFillBlit(struct intel_context *intel,
OUT_BATCH((y << 16) | x);
OUT_BATCH(((y + h) << 16) | (x + w));
OUT_RELOC(dst_buffer,
DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
dst_offset);
OUT_BATCH(color);
ADVANCE_BATCH();
@@ -347,12 +347,12 @@ intelEmitCopyBlit(struct intel_context *intel,
OUT_BATCH((dst_y << 16) | dst_x);
OUT_BATCH((dst_y2 << 16) | dst_x2);
OUT_RELOC(dst_buffer,
DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
dst_offset);
OUT_BATCH((src_y << 16) | src_x);
OUT_BATCH(src_pitch);
OUT_RELOC(src_buffer,
DRM_GEM_DOMAIN_I915_RENDER, 0,
I915_GEM_DOMAIN_RENDER, 0,
src_offset);
ADVANCE_BATCH();
}
@@ -366,12 +366,12 @@ intelEmitCopyBlit(struct intel_context *intel,
OUT_BATCH((0 << 16) | dst_x);
OUT_BATCH((h << 16) | dst_x2);
OUT_RELOC(dst_buffer,
DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
dst_offset + dst_y * dst_pitch);
OUT_BATCH((0 << 16) | src_x);
OUT_BATCH(src_pitch);
OUT_RELOC(src_buffer,
DRM_GEM_DOMAIN_I915_RENDER, 0,
I915_GEM_DOMAIN_RENDER, 0,
src_offset + src_y * src_pitch);
ADVANCE_BATCH();
}
@@ -551,7 +551,7 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask)
OUT_BATCH((b.y1 << 16) | b.x1);
OUT_BATCH((b.y2 << 16) | b.x2);
OUT_RELOC(write_buffer,
DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
irb_region->draw_offset);
OUT_BATCH(clearVal);
ADVANCE_BATCH();
@@ -624,7 +624,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
OUT_RELOC(dst_buffer,
DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
dst_offset);
OUT_BATCH(0); /* bg */
OUT_BATCH(fg_color); /* fg */