radeonsi: replace ac_nir_lower_subdword_loads
ac_nir_lower_mem_access_bit_sizes() does the work of it. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32781>
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@@ -2614,8 +2614,13 @@ static struct nir_shader *si_get_nir_shader(struct si_shader *shader, struct si_
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});
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NIR_PASS(progress, nir, nir_opt_shrink_stores, false);
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nir_divergence_analysis(nir);
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NIR_PASS(progress, nir, ac_nir_flag_smem_for_loads, sel->screen->info.gfx_level,
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!nir->info.use_aco_amd, false);
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NIR_PASS(progress, nir, ac_nir_lower_mem_access_bit_sizes,
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sel->screen->info.gfx_level, !nir->info.use_aco_amd);
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if (sel->stage == MESA_SHADER_KERNEL) {
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NIR_PASS(progress, nir, ac_nir_lower_mem_access_bit_sizes, sel->screen->info.gfx_level, !nir->info.use_aco_amd);
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NIR_PASS(progress, nir, ac_nir_lower_global_access);
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if (nir->info.bit_sizes_int & (8 | 16)) {
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@@ -415,11 +415,6 @@ char *si_finalize_nir(struct pipe_screen *screen, struct nir_shader *nir)
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if (nir->info.stage == MESA_SHADER_FRAGMENT)
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NIR_PASS_V(nir, nir_lower_color_inputs);
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NIR_PASS_V(nir, ac_nir_lower_subdword_loads,
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(ac_nir_lower_subdword_options) {
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.modes_1_comp = nir_var_mem_ubo,
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.modes_N_comps = nir_var_mem_ubo | nir_var_mem_ssbo
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});
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NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_shared, nir_address_format_32bit_offset);
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/* Remove dead derefs, so that we can remove uniforms. */
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