freedreno/a3xx: disable early-z when we have kill's

Signed-off-by: Rob Clark <robclark@freedesktop.org>

src/gallium/drivers/freedreno/a3xx/fd3_emit.c

@@ -454,6 +454,9 @@ fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 			val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
 			val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
 		}
+		if (fp->has_kill) {
+			val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
+		}
 		OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 		OUT_RING(ring, val);
 	}

src/gallium/drivers/freedreno/ir3/ir3_compiler.c

@@ -2047,6 +2047,8 @@ trans_kill(const struct instr_translater *t,
 	ir3_reg_create(instr, 0, IR3_REG_SSA)->instr = cond;
 
 	ctx->kill[ctx->kill_count++] = instr;
+
+	ctx->so->has_kill = true;
 }
 
 /*
@@ -2081,6 +2083,8 @@ trans_killif(const struct instr_translater *t,
 
 	ctx->kill[ctx->kill_count++] = instr;
 
+	ctx->so->has_kill = true;
+
 }
 /*
  * I2F / U2F / F2I / F2U

src/gallium/drivers/freedreno/ir3/ir3_shader.h

@@ -171,6 +171,9 @@ struct ir3_shader_variant {
 	/* do we have one or more texture sample instructions: */
 	bool has_samp;
 
+	/* do we have kill instructions: */
+	bool has_kill;
+
 	/* const reg # of first immediate, ie. 1 == c1
 	 * (not regid, because TGSI thinks in terms of vec4 registers,
 	 * not scalar registers)