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anv: Set all async compute registers in STATE_COMPUTE_MODE

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Setting the missing registers to specification recommended values that
is also the default value, so it is not expected any changes in
behavior or performance here.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30796>
This commit is contained in:
José Roberto de Souza
2024-08-22 07:38:33 -07:00
committed by Marge Bot
parent 86ed5ec78e
commit 3efba707bf
1 changed files with 7 additions and 1 deletions
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src/intel/vulkan/genX_init_state.c
+7 -1
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@@ -752,8 +752,14 @@ init_compute_queue_state(struct anv_queue *queue)
anv_batch_emit(batch, GENX(STATE_COMPUTE_MODE), cm) {
#if GFX_VER < 20
cm.PixelAsyncComputeThreadLimit = 4;
cm.PixelAsyncComputeThreadLimit = PACTL_Max24;
cm.ZPassAsyncComputeThreadLimit = ZPACTL_Max60;
cm.PixelAsyncComputeThreadLimitMask = 0x7;
cm.ZPassAsyncComputeThreadLimitMask = 0x7;
if (intel_device_info_is_mtl_or_arl(devinfo)) {
cm.ZAsyncThrottlesettings = ZATS_DefertoPixelAsyncComputeThreadLimit;
cm.ZAsyncThrottlesettingsMask = 0x3;
}
#endif
}
#endif