From 3efba707bf879f25f2e2a8c879b162734bdcf7c6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= Date: Thu, 22 Aug 2024 07:38:33 -0700 Subject: [PATCH] anv: Set all async compute registers in STATE_COMPUTE_MODE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Setting the missing registers to specification recommended values that is also the default value, so it is not expected any changes in behavior or performance here. Reviewed-by: Paulo Zanoni Signed-off-by: José Roberto de Souza Part-of: --- src/intel/vulkan/genX_init_state.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/intel/vulkan/genX_init_state.c b/src/intel/vulkan/genX_init_state.c index b6a27b7b231..251ab0aed1a 100644 --- a/src/intel/vulkan/genX_init_state.c +++ b/src/intel/vulkan/genX_init_state.c @@ -752,8 +752,14 @@ init_compute_queue_state(struct anv_queue *queue) anv_batch_emit(batch, GENX(STATE_COMPUTE_MODE), cm) { #if GFX_VER < 20 - cm.PixelAsyncComputeThreadLimit = 4; + cm.PixelAsyncComputeThreadLimit = PACTL_Max24; + cm.ZPassAsyncComputeThreadLimit = ZPACTL_Max60; cm.PixelAsyncComputeThreadLimitMask = 0x7; + cm.ZPassAsyncComputeThreadLimitMask = 0x7; + if (intel_device_info_is_mtl_or_arl(devinfo)) { + cm.ZAsyncThrottlesettings = ZATS_DefertoPixelAsyncComputeThreadLimit; + cm.ZAsyncThrottlesettingsMask = 0x3; + } #endif } #endif