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radv/meta: add a helper to create pipeline layout

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30187>
This commit is contained in:
Samuel Pitoiset
2024-07-12 12:07:27 +02:00
committed by Marge Bot
parent c6a626e000
commit 3d322b787e
18 changed files with 132 additions and 267 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/meta/radv_meta.c
+16
View File
@@ -743,3 +743,19 @@ radv_meta_create_compute_pipeline(struct radv_device *device, nir_shader *nir, V
return radv_compute_pipeline_create(radv_device_to_handle(device), device->meta_state.cache, &pipeline_info, NULL,
pipeline);
}
VkResult
radv_meta_create_pipeline_layout(struct radv_device *device, VkDescriptorSetLayout *set_layout, uint32_t num_pc_ranges,
const VkPushConstantRange *pc_ranges, VkPipelineLayout *pipeline_layout)
{
const VkPipelineLayoutCreateInfo pipeline_layout_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = !!set_layout,
.pSetLayouts = set_layout,
.pushConstantRangeCount = num_pc_ranges,
.pPushConstantRanges = pc_ranges,
};
return radv_CreatePipelineLayout(radv_device_to_handle(device), &pipeline_layout_info, &device->meta_state.alloc,
pipeline_layout);
}
src/amd/vulkan/meta/radv_meta.h
+4
View File
@@ -311,6 +311,10 @@ void radv_depth_stencil_resolve_rendering_fs(struct radv_cmd_buffer *cmd_buffer,
VkResult radv_meta_create_compute_pipeline(struct radv_device *device, nir_shader *nir,
VkPipelineLayout pipeline_layout, VkPipeline *pipeline);
VkResult radv_meta_create_pipeline_layout(struct radv_device *device, VkDescriptorSetLayout *set_layout,
uint32_t num_pc_ranges, const VkPushConstantRange *pc_ranges,
VkPipelineLayout *pipeline_layout);
#ifdef __cplusplus
}
#endif
src/amd/vulkan/meta/radv_meta_blit.c
+2 -9
View File
@@ -842,15 +842,8 @@ radv_device_init_meta_blit_state(struct radv_device *device, bool on_demand)
const VkPushConstantRange push_constant_range = {VK_SHADER_STAGE_VERTEX_BIT, 0, 20};
result = radv_CreatePipelineLayout(radv_device_to_handle(device),
&(VkPipelineLayoutCreateInfo){
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 1,
.pSetLayouts = &device->meta_state.blit.ds_layout,
.pushConstantRangeCount = 1,
.pPushConstantRanges = &push_constant_range,
},
&device->meta_state.alloc, &device->meta_state.blit.pipeline_layout);
result = radv_meta_create_pipeline_layout(device, &device->meta_state.blit.ds_layout, 1, &push_constant_range,
&device->meta_state.blit.pipeline_layout);
if (result != VK_SUCCESS)
return result;
src/amd/vulkan/meta/radv_meta_blit2d.c
+2 -10
View File
@@ -1011,16 +1011,8 @@ meta_blit2d_create_pipe_layout(struct radv_device *device, int idx, uint32_t log
if (result != VK_SUCCESS)
goto fail;
result =
radv_CreatePipelineLayout(radv_device_to_handle(device),
&(VkPipelineLayoutCreateInfo){
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 1,
.pSetLayouts = &device->meta_state.blit2d[log2_samples].ds_layouts[idx],
.pushConstantRangeCount = num_push_constant_range,
.pPushConstantRanges = push_constant_ranges,
},
&device->meta_state.alloc, &device->meta_state.blit2d[log2_samples].p_layouts[idx]);
result = radv_meta_create_pipeline_layout(device,
&device->meta_state.blit2d[log2_samples].ds_layouts[idx], num_push_constant_range, push_constant_ranges, &device->meta_state.blit2d[log2_samples].p_layouts[idx]);
if (result != VK_SUCCESS)
goto fail;
return VK_SUCCESS;
src/amd/vulkan/meta/radv_meta_buffer.c
+8 -14
View File
@@ -72,27 +72,21 @@ radv_device_init_meta_buffer_state(struct radv_device *device)
nir_shader *fill_cs = build_buffer_fill_shader(device);
nir_shader *copy_cs = build_buffer_copy_shader(device);
VkPipelineLayoutCreateInfo fill_pl_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 0,
.pushConstantRangeCount = 1,
.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(struct fill_constants)},
const VkPushConstantRange pc_range_fill = {
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
.size = sizeof(struct fill_constants),
};
result = radv_CreatePipelineLayout(radv_device_to_handle(device), &fill_pl_create_info, &device->meta_state.alloc,
&device->meta_state.buffer.fill_p_layout);
result = radv_meta_create_pipeline_layout(device, NULL, 1, &pc_range_fill, &device->meta_state.buffer.fill_p_layout);
if (result != VK_SUCCESS)
goto fail;
VkPipelineLayoutCreateInfo copy_pl_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 0,
.pushConstantRangeCount = 1,
.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(struct copy_constants)},
const VkPushConstantRange pc_range_copy = {
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
.size = sizeof(struct copy_constants),
};
result = radv_CreatePipelineLayout(radv_device_to_handle(device), &copy_pl_create_info, &device->meta_state.alloc,
&device->meta_state.buffer.copy_p_layout);
result = radv_meta_create_pipeline_layout(device, NULL, 1, &pc_range_copy, &device->meta_state.buffer.copy_p_layout);
if (result != VK_SUCCESS)
goto fail;
src/amd/vulkan/meta/radv_meta_bufimage.c
+35 -56
View File
@@ -84,16 +84,13 @@ radv_device_init_meta_itob_state(struct radv_device *device)
if (result != VK_SUCCESS)
goto fail;
VkPipelineLayoutCreateInfo pl_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 1,
.pSetLayouts = &device->meta_state.itob.img_ds_layout,
.pushConstantRangeCount = 1,
.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16},
const VkPushConstantRange pc_range = {
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
.size = 16,
};
result = radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info, &device->meta_state.alloc,
&device->meta_state.itob.img_p_layout);
result = radv_meta_create_pipeline_layout(device, &device->meta_state.itob.img_ds_layout, 1, &pc_range,
&device->meta_state.itob.img_p_layout);
if (result != VK_SUCCESS)
goto fail;
@@ -198,16 +195,13 @@ radv_device_init_meta_btoi_state(struct radv_device *device)
if (result != VK_SUCCESS)
goto fail;
VkPipelineLayoutCreateInfo pl_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 1,
.pSetLayouts = &device->meta_state.btoi.img_ds_layout,
.pushConstantRangeCount = 1,
.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16},
const VkPushConstantRange pc_range = {
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
.size = 16,
};
result = radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info, &device->meta_state.alloc,
&device->meta_state.btoi.img_p_layout);
result = radv_meta_create_pipeline_layout(device, &device->meta_state.btoi.img_ds_layout, 1,
&pc_range, &device->meta_state.btoi.img_p_layout);
if (result != VK_SUCCESS)
goto fail;
@@ -316,16 +310,13 @@ radv_device_init_meta_btoi_r32g32b32_state(struct radv_device *device)
if (result != VK_SUCCESS)
goto fail;
VkPipelineLayoutCreateInfo pl_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 1,
.pSetLayouts = &device->meta_state.btoi_r32g32b32.img_ds_layout,
.pushConstantRangeCount = 1,
.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16},
const VkPushConstantRange pc_range = {
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
.size = 16,
};
result = radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info, &device->meta_state.alloc,
&device->meta_state.btoi_r32g32b32.img_p_layout);
result = radv_meta_create_pipeline_layout(device, &device->meta_state.btoi_r32g32b32.img_ds_layout, 1, &pc_range,
&device->meta_state.btoi_r32g32b32.img_p_layout);
if (result != VK_SUCCESS)
goto fail;
@@ -441,16 +432,13 @@ radv_device_init_meta_itoi_state(struct radv_device *device)
if (result != VK_SUCCESS)
goto fail;
VkPipelineLayoutCreateInfo pl_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 1,
.pSetLayouts = &device->meta_state.itoi.img_ds_layout,
.pushConstantRangeCount = 1,
.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 24},
const VkPushConstantRange pc_range = {
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
.size = 24,
};
result = radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info, &device->meta_state.alloc,
&device->meta_state.itoi.img_p_layout);
result = radv_meta_create_pipeline_layout(device, &device->meta_state.itoi.img_ds_layout, 1, &pc_range,
&device->meta_state.itoi.img_p_layout);
if (result != VK_SUCCESS)
goto fail;
@@ -585,16 +573,13 @@ radv_device_init_meta_itoi_r32g32b32_state(struct radv_device *device)
if (result != VK_SUCCESS)
goto fail;
VkPipelineLayoutCreateInfo pl_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 1,
.pSetLayouts = &device->meta_state.itoi_r32g32b32.img_ds_layout,
.pushConstantRangeCount = 1,
.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 24},
const VkPushConstantRange pc_range = {
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
.size = 24,
};
result = radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info, &device->meta_state.alloc,
&device->meta_state.itoi_r32g32b32.img_p_layout);
result = radv_meta_create_pipeline_layout(device, &device->meta_state.itoi_r32g32b32.img_ds_layout, 1, &pc_range,
&device->meta_state.itoi_r32g32b32.img_p_layout);
if (result != VK_SUCCESS)
goto fail;
@@ -686,16 +671,13 @@ radv_device_init_meta_cleari_state(struct radv_device *device)
if (result != VK_SUCCESS)
goto fail;
VkPipelineLayoutCreateInfo pl_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 1,
.pSetLayouts = &device->meta_state.cleari.img_ds_layout,
.pushConstantRangeCount = 1,
.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 20},
const VkPushConstantRange pc_range = {
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
.size = 20,
};
result = radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info, &device->meta_state.alloc,
&device->meta_state.cleari.img_p_layout);
result = radv_meta_create_pipeline_layout(device, &device->meta_state.cleari.img_ds_layout, 1, &pc_range,
&device->meta_state.cleari.img_p_layout);
if (result != VK_SUCCESS)
goto fail;
@@ -790,16 +772,13 @@ radv_device_init_meta_cleari_r32g32b32_state(struct radv_device *device)
if (result != VK_SUCCESS)
goto fail;
VkPipelineLayoutCreateInfo pl_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 1,
.pSetLayouts = &device->meta_state.cleari_r32g32b32.img_ds_layout,
.pushConstantRangeCount = 1,
.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16},
const VkPushConstantRange pc_range = {
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
.size = 16,
};
result = radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info, &device->meta_state.alloc,
&device->meta_state.cleari_r32g32b32.img_p_layout);
result = radv_meta_create_pipeline_layout(device, &device->meta_state.cleari_r32g32b32.img_ds_layout, 1, &pc_range,
&device->meta_state.cleari_r32g32b32.img_p_layout);
if (result != VK_SUCCESS)
goto fail;
src/amd/vulkan/meta/radv_meta_clear.c
+23 -47
View File
@@ -844,21 +844,13 @@ init_meta_clear_htile_mask_state(struct radv_device *device)
if (result != VK_SUCCESS)
goto fail;
VkPipelineLayoutCreateInfo p_layout_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 1,
.pSetLayouts = &state->clear_htile_mask_ds_layout,
.pushConstantRangeCount = 1,
.pPushConstantRanges =
&(VkPushConstantRange){
VK_SHADER_STAGE_COMPUTE_BIT,
0,
8,
},
const VkPushConstantRange pc_range = {
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
.size = 8,
};
result = radv_CreatePipelineLayout(radv_device_to_handle(device), &p_layout_info, &state->alloc,
&state->clear_htile_mask_p_layout);
result = radv_meta_create_pipeline_layout(device, &state->clear_htile_mask_ds_layout, 1, &pc_range,
&state->clear_htile_mask_p_layout);
if (result != VK_SUCCESS)
goto fail;
@@ -948,21 +940,13 @@ init_meta_clear_dcc_comp_to_single_state(struct radv_device *device)
if (result != VK_SUCCESS)
goto fail;
VkPipelineLayoutCreateInfo p_layout_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 1,
.pSetLayouts = &state->clear_dcc_comp_to_single_ds_layout,
.pushConstantRangeCount = 1,
.pPushConstantRanges =
&(VkPushConstantRange){
VK_SHADER_STAGE_COMPUTE_BIT,
0,
24,
},
const VkPushConstantRange pc_range = {
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
.size = 24,
};
result = radv_CreatePipelineLayout(radv_device_to_handle(device), &p_layout_info, &state->alloc,
&state->clear_dcc_comp_to_single_p_layout);
result = radv_meta_create_pipeline_layout(device, &state->clear_dcc_comp_to_single_ds_layout, 1, &pc_range,
&state->clear_dcc_comp_to_single_p_layout);
if (result != VK_SUCCESS)
goto fail;
@@ -982,39 +966,31 @@ radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand)
VkResult res;
struct radv_meta_state *state = &device->meta_state;
VkPipelineLayoutCreateInfo pl_color_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 0,
.pushConstantRangeCount = 1,
.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
const VkPushConstantRange pc_range_color = {
.stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
.size = 16,
};
res = radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_color_create_info, &device->meta_state.alloc,
&device->meta_state.clear_color_p_layout);
res = radv_meta_create_pipeline_layout(device, NULL, 1, &pc_range_color, &device->meta_state.clear_color_p_layout);
if (res != VK_SUCCESS)
return res;
VkPipelineLayoutCreateInfo pl_depth_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 0,
.pushConstantRangeCount = 1,
.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
const VkPushConstantRange pc_range_depth = {
.stageFlags = VK_SHADER_STAGE_VERTEX_BIT,
.size = 4,
};
res = radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_depth_create_info, &device->meta_state.alloc,
&device->meta_state.clear_depth_p_layout);
res = radv_meta_create_pipeline_layout(device, NULL, 1, &pc_range_depth, &device->meta_state.clear_depth_p_layout);
if (res != VK_SUCCESS)
return res;
VkPipelineLayoutCreateInfo pl_depth_unrestricted_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 0,
.pushConstantRangeCount = 1,
.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 4},
const VkPushConstantRange pc_range_depth_unrestricted = {
.stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
.size = 4,
};
res = radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_depth_unrestricted_create_info,
&device->meta_state.alloc, &device->meta_state.clear_depth_unrestricted_p_layout);
res = radv_meta_create_pipeline_layout(device, NULL, 1, &pc_range_depth_unrestricted,
&device->meta_state.clear_depth_unrestricted_p_layout);
if (res != VK_SUCCESS)
return res;
src/amd/vulkan/meta/radv_meta_copy_vrs_htile.c
+5 -13
View File
@@ -131,21 +131,13 @@ radv_device_init_meta_copy_vrs_htile_state(struct radv_device *device, struct ra
if (result != VK_SUCCESS)
goto fail;
VkPipelineLayoutCreateInfo p_layout_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 1,
.pSetLayouts = &state->copy_vrs_htile_ds_layout,
.pushConstantRangeCount = 1,
.pPushConstantRanges =
&(VkPushConstantRange){
VK_SHADER_STAGE_COMPUTE_BIT,
0,
20,
},
const VkPushConstantRange pc_range = {
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
.size = 20,
};
result = radv_CreatePipelineLayout(radv_device_to_handle(device), &p_layout_info, &state->alloc,
&state->copy_vrs_htile_p_layout);
result = radv_meta_create_pipeline_layout(device, &state->copy_vrs_htile_ds_layout, 1, &pc_range,
&state->copy_vrs_htile_p_layout);
if (result != VK_SUCCESS)
goto fail;
src/amd/vulkan/meta/radv_meta_dcc_retile.c
+5 -8
View File
@@ -110,16 +110,13 @@ radv_device_init_meta_dcc_retile_state(struct radv_device *device, struct radeon
if (result != VK_SUCCESS)
goto cleanup;
VkPipelineLayoutCreateInfo pl_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 1,
.pSetLayouts = &device->meta_state.dcc_retile.ds_layout,
.pushConstantRangeCount = 1,
.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16},
const VkPushConstantRange pc_range = {
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
.size = 16,
};
result = radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info, &device->meta_state.alloc,
&device->meta_state.dcc_retile.p_layout);
result = radv_meta_create_pipeline_layout(device, &device->meta_state.dcc_retile.ds_layout, 1, &pc_range,
&device->meta_state.dcc_retile.p_layout);
if (result != VK_SUCCESS)
goto cleanup;
src/amd/vulkan/meta/radv_meta_decompress.c
+3 -25
View File
@@ -82,16 +82,8 @@ create_expand_depth_stencil_compute(struct radv_device *device)
if (result != VK_SUCCESS)
goto cleanup;
VkPipelineLayoutCreateInfo pl_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 1,
.pSetLayouts = &device->meta_state.expand_depth_stencil_compute_ds_layout,
.pushConstantRangeCount = 0,
.pPushConstantRanges = NULL,
};
result = radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info, &device->meta_state.alloc,
&device->meta_state.expand_depth_stencil_compute_p_layout);
result = radv_meta_create_pipeline_layout(device, &device->meta_state.expand_depth_stencil_compute_ds_layout, 0,
NULL, &device->meta_state.expand_depth_stencil_compute_p_layout);
if (result != VK_SUCCESS)
goto cleanup;
@@ -105,20 +97,6 @@ cleanup:
return result;
}
static VkResult
create_pipeline_layout(struct radv_device *device, VkPipelineLayout *layout)
{
VkPipelineLayoutCreateInfo pl_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 0,
.pSetLayouts = NULL,
.pushConstantRangeCount = 0,
.pPushConstantRanges = NULL,
};
return radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info, &device->meta_state.alloc, layout);
}
static VkResult
create_pipeline(struct radv_device *device, uint32_t samples, VkPipelineLayout layout, enum radv_depth_op op,
VkPipeline *pipeline)
@@ -284,7 +262,7 @@ radv_device_init_meta_depth_decomp_state(struct radv_device *device, bool on_dem
for (uint32_t i = 0; i < ARRAY_SIZE(state->depth_decomp); ++i) {
uint32_t samples = 1 << i;
res = create_pipeline_layout(device, &state->depth_decomp[i].p_layout);
res = radv_meta_create_pipeline_layout(device, NULL, 0, NULL, &state->depth_decomp[i].p_layout);
if (res != VK_SUCCESS)
return res;
src/amd/vulkan/meta/radv_meta_fast_clear.c
+4 -25
View File
@@ -80,16 +80,9 @@ create_dcc_compress_compute(struct radv_device *device)
if (result != VK_SUCCESS)
goto cleanup;
VkPipelineLayoutCreateInfo pl_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 1,
.pSetLayouts = &device->meta_state.fast_clear_flush.dcc_decompress_compute_ds_layout,
.pushConstantRangeCount = 0,
.pPushConstantRanges = NULL,
};
result = radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info, &device->meta_state.alloc,
&device->meta_state.fast_clear_flush.dcc_decompress_compute_p_layout);
result =
radv_meta_create_pipeline_layout(device, &device->meta_state.fast_clear_flush.dcc_decompress_compute_ds_layout, 0,
NULL, &device->meta_state.fast_clear_flush.dcc_decompress_compute_p_layout);
if (result != VK_SUCCESS)
goto cleanup;
@@ -104,20 +97,6 @@ cleanup:
return result;
}
static VkResult
create_pipeline_layout(struct radv_device *device, VkPipelineLayout *layout)
{
VkPipelineLayoutCreateInfo pl_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 0,
.pSetLayouts = NULL,
.pushConstantRangeCount = 0,
.pPushConstantRanges = NULL,
};
return radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info, &device->meta_state.alloc, layout);
}
static VkResult
create_pipeline(struct radv_device *device, VkShaderModule vs_module_h, VkPipelineLayout layout)
{
@@ -379,7 +358,7 @@ radv_device_init_meta_fast_clear_flush_state_internal(struct radv_device *device
goto cleanup;
}
res = create_pipeline_layout(device, &device->meta_state.fast_clear_flush.p_layout);
res = radv_meta_create_pipeline_layout(device, NULL, 0, NULL, &device->meta_state.fast_clear_flush.p_layout);
if (res != VK_SUCCESS)
goto cleanup;
src/amd/vulkan/meta/radv_meta_fmask_copy.c
+2 -8
View File
@@ -141,14 +141,8 @@ radv_device_init_meta_fmask_copy_state_internal(struct radv_device *device, uint
}
if (!device->meta_state.fmask_copy.p_layout) {
VkPipelineLayoutCreateInfo pl_create_info = {.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 1,
.pSetLayouts = &device->meta_state.fmask_copy.ds_layout,
.pushConstantRangeCount = 0,
.pPushConstantRanges = NULL};
result = radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info, &device->meta_state.alloc,
&device->meta_state.fmask_copy.p_layout);
result = radv_meta_create_pipeline_layout(device, &device->meta_state.fmask_copy.ds_layout, 0, NULL,
&device->meta_state.fmask_copy.p_layout);
if (result != VK_SUCCESS)
return result;
}
src/amd/vulkan/meta/radv_meta_fmask_expand.c
+2 -10
View File
@@ -193,16 +193,8 @@ radv_device_init_meta_fmask_expand_state_internal(struct radv_device *device, ui
}
if (!state->fmask_expand.p_layout) {
VkPipelineLayoutCreateInfo color_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 1,
.pSetLayouts = &state->fmask_expand.ds_layout,
.pushConstantRangeCount = 0,
.pPushConstantRanges = NULL,
};
result = radv_CreatePipelineLayout(radv_device_to_handle(device), &color_create_info, &state->alloc,
&state->fmask_expand.p_layout);
result = radv_meta_create_pipeline_layout(device, &state->fmask_expand.ds_layout, 0, NULL,
&state->fmask_expand.p_layout);
if (result != VK_SUCCESS)
return result;
}
src/amd/vulkan/meta/radv_meta_resolve.c
+1 -10
View File
@@ -41,17 +41,8 @@ create_pipeline(struct radv_device *device, VkShaderModule vs_module_h, VkFormat
goto cleanup;
}
VkPipelineLayoutCreateInfo pl_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 0,
.pSetLayouts = NULL,
.pushConstantRangeCount = 0,
.pPushConstantRanges = NULL,
};
if (!device->meta_state.resolve.p_layout) {
result = radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info, &device->meta_state.alloc,
&device->meta_state.resolve.p_layout);
result = radv_meta_create_pipeline_layout(device, NULL, 0, NULL, &device->meta_state.resolve.p_layout);
if (result != VK_SUCCESS)
goto cleanup;
}
src/amd/vulkan/meta/radv_meta_resolve_cs.c
+5 -8
View File
@@ -191,16 +191,13 @@ create_layout(struct radv_device *device)
if (result != VK_SUCCESS)
goto fail;
VkPipelineLayoutCreateInfo pl_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 1,
.pSetLayouts = &device->meta_state.resolve_compute.ds_layout,
.pushConstantRangeCount = 1,
.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16},
const VkPushConstantRange pc_range = {
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
.size = 16,
};
result = radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info, &device->meta_state.alloc,
&device->meta_state.resolve_compute.p_layout);
result = radv_meta_create_pipeline_layout(device, &device->meta_state.resolve_compute.ds_layout, 1, &pc_range,
&device->meta_state.resolve_compute.p_layout);
if (result != VK_SUCCESS)
goto fail;
return VK_SUCCESS;
src/amd/vulkan/meta/radv_meta_resolve_fs.c
+5 -8
View File
@@ -67,16 +67,13 @@ create_layout(struct radv_device *device)
if (result != VK_SUCCESS)
goto fail;
VkPipelineLayoutCreateInfo pl_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 1,
.pSetLayouts = &device->meta_state.resolve_fragment.ds_layout,
.pushConstantRangeCount = 1,
.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 8},
const VkPushConstantRange pc_range = {
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
.size = 8,
};
result = radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info, &device->meta_state.alloc,
&device->meta_state.resolve_fragment.p_layout);
result = radv_meta_create_pipeline_layout(device, &device->meta_state.resolve_fragment.ds_layout, 1, &pc_range,
&device->meta_state.resolve_fragment.p_layout);
if (result != VK_SUCCESS)
goto fail;
return VK_SUCCESS;
src/amd/vulkan/radv_device_generated_commands.c
+5 -8
View File
@@ -2097,16 +2097,13 @@ radv_device_init_dgc_prepare_state(struct radv_device *device)
if (result != VK_SUCCESS)
goto cleanup;
const VkPipelineLayoutCreateInfo leaf_pl_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 1,
.pSetLayouts = &device->meta_state.dgc_prepare.ds_layout,
.pushConstantRangeCount = 1,
.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(struct radv_dgc_params)},
const VkPushConstantRange pc_range = {
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
.size = sizeof(struct radv_dgc_params),
};
result = radv_CreatePipelineLayout(radv_device_to_handle(device), &leaf_pl_create_info, &device->meta_state.alloc,
&device->meta_state.dgc_prepare.p_layout);
result = radv_meta_create_pipeline_layout(device, &device->meta_state.dgc_prepare.ds_layout, 1, &pc_range,
&device->meta_state.dgc_prepare.p_layout);
if (result != VK_SUCCESS)
goto cleanup;
src/amd/vulkan/radv_query.c
+5 -8
View File
@@ -914,16 +914,13 @@ radv_device_init_meta_query_state_internal(struct radv_device *device)
if (result != VK_SUCCESS)
goto fail;
VkPipelineLayoutCreateInfo occlusion_pl_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 1,
.pSetLayouts = &device->meta_state.query.ds_layout,
.pushConstantRangeCount = 1,
.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 20},
const VkPushConstantRange pc_range = {
.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
.size = 20,
};
result = radv_CreatePipelineLayout(radv_device_to_handle(device), &occlusion_pl_create_info,
&device->meta_state.alloc, &device->meta_state.query.p_layout);
result = radv_meta_create_pipeline_layout(device, &device->meta_state.query.ds_layout, 1, &pc_range,
&device->meta_state.query.p_layout);
if (result != VK_SUCCESS)
goto fail;