freedreno: extract helper for stage->sb for a4xx+

Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark
2017-04-05 19:43:31 -04:00
parent 9567beab36
commit 3c5d309477
5 changed files with 29 additions and 28 deletions
@@ -45,11 +45,6 @@
#include "fd4_format.h"
#include "fd4_zsa.h"
static const enum a4xx_state_block sb[] = {
[SHADER_VERTEX] = SB4_VS_SHADER,
[SHADER_FRAGMENT] = SB4_FS_SHADER,
};
/* regid: base const register
* prsc or dwords: buffer containing constant values
* sizedwords: size of const value buffer
@@ -76,7 +71,7 @@ fd4_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
OUT_PKT3(ring, CP_LOAD_STATE4, 2 + sz);
OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
CP_LOAD_STATE4_0_STATE_SRC(src) |
CP_LOAD_STATE4_0_STATE_BLOCK(sb[type]) |
CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
CP_LOAD_STATE4_0_NUM_UNIT(sizedwords/4));
if (prsc) {
struct fd_bo *bo = fd_resource(prsc)->bo;
@@ -104,7 +99,7 @@ fd4_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
OUT_PKT3(ring, CP_LOAD_STATE4, 2 + anum);
OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
CP_LOAD_STATE4_0_STATE_BLOCK(sb[type]) |
CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
CP_LOAD_STATE4_0_NUM_UNIT(anum/4));
OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
@@ -89,16 +89,10 @@ static void
emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
{
const struct ir3_info *si = &so->info;
enum adreno_state_block sb;
enum a4xx_state_block sb = fd4_stage2shadersb(so->type);
enum adreno_state_src src;
uint32_t i, sz, *bin;
if (so->type == SHADER_VERTEX) {
sb = SB4_VS_SHADER;
} else {
sb = SB4_FS_SHADER;
}
if (fd_mesa_debug & FD_DBG_DIRECT) {
sz = si->sizedwords;
src = SS4_DIRECT;
@@ -43,11 +43,6 @@
#include "fd5_format.h"
#include "fd5_zsa.h"
static const enum a4xx_state_block sb[] = {
[SHADER_VERTEX] = SB4_VS_SHADER,
[SHADER_FRAGMENT] = SB4_FS_SHADER,
};
/* regid: base const register
* prsc or dwords: buffer containing constant values
* sizedwords: size of const value buffer
@@ -74,7 +69,7 @@ fd5_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
OUT_PKT7(ring, CP_LOAD_STATE4, 3 + sz);
OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
CP_LOAD_STATE4_0_STATE_SRC(src) |
CP_LOAD_STATE4_0_STATE_BLOCK(sb[type]) |
CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
CP_LOAD_STATE4_0_NUM_UNIT(sizedwords/4));
if (prsc) {
struct fd_bo *bo = fd_resource(prsc)->bo;
@@ -103,7 +98,7 @@ fd5_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * anum));
OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
CP_LOAD_STATE4_0_STATE_BLOCK(sb[type]) |
CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
CP_LOAD_STATE4_0_NUM_UNIT(anum/2));
OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
@@ -88,16 +88,10 @@ static void
emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
{
const struct ir3_info *si = &so->info;
enum a4xx_state_block sb;
enum a4xx_state_block sb = fd4_stage2shadersb(so->type);
enum a4xx_state_src src;
uint32_t i, sz, *bin;
if (so->type == SHADER_VERTEX) {
sb = SB4_VS_SHADER;
} else {
sb = SB4_FS_SHADER;
}
if (fd_mesa_debug & FD_DBG_DIRECT) {
sz = si->sizedwords;
src = SS4_DIRECT;
@@ -449,4 +449,27 @@ pack_rgba(enum pipe_format format, const float *rgba)
#define foreach_bit(b, mask) \
for (uint32_t _m = (mask); _m && ({(b) = u_bit_scan(&_m); 1;});)
#define BIT(bit) (1u << bit)
/*
* a4xx+ helpers:
*/
static inline enum a4xx_state_block
fd4_stage2shadersb(enum shader_t type)
{
switch (type) {
case SHADER_VERTEX:
return SB4_VS_SHADER;
case SHADER_FRAGMENT:
return SB4_FS_SHADER;
case SHADER_COMPUTE:
return SB4_CS_SHADER;
default:
unreachable("bad shader type");
return ~0;
}
}
#endif /* FREEDRENO_UTIL_H_ */