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radv: fix SPI_SHADER_Z_FORMAT for alpha-to-coverage via MRTZ on GFX11

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It should select a 32-bit format with alpha.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20126>
This commit is contained in:
Samuel Pitoiset
2022-12-02 08:29:35 +01:00
committed by Marge Bot
parent a297ac10a4
commit 3ab9218820
3 changed files with 12 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/radv_pipeline.c
+1 -1
View File
@@ -4867,7 +4867,7 @@ radv_pipeline_emit_fragment_shader(struct radeon_cmdbuf *ctx_cs, struct radeon_c
radeon_set_context_reg(
ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
ac_get_spi_shader_z_format(ps->info.ps.writes_z, ps->info.ps.writes_stencil,
ps->info.ps.writes_sample_mask, false));
ps->info.ps.writes_sample_mask, ps->info.ps.writes_mrt0_alpha));
struct radv_userdata_info *loc =
radv_lookup_user_sgpr(&pipeline->base, MESA_SHADER_FRAGMENT, AC_UD_PS_NUM_SAMPLES);
src/amd/vulkan/radv_shader.h
+2
View File
@@ -300,6 +300,7 @@ struct radv_shader_info {
bool writes_z;
bool writes_stencil;
bool writes_sample_mask;
bool writes_mrt0_alpha;
bool has_pcoord;
bool prim_id_input;
bool layer_input;
@@ -333,6 +334,7 @@ struct radv_shader_info {
bool has_epilog;
unsigned spi_ps_input;
unsigned colors_written;
uint8_t color0_written;
} ps;
struct {
bool uses_grid_size;
src/amd/vulkan/radv_shader_info.c
+9 -1
View File
@@ -78,8 +78,12 @@ gather_intrinsic_store_output_info(const nir_shader *nir, const nir_intrinsic_in
output_usage_mask = info->gs.output_usage_mask;
break;
case MESA_SHADER_FRAGMENT:
if (idx >= FRAG_RESULT_DATA0)
if (idx >= FRAG_RESULT_DATA0) {
info->ps.colors_written |= 0xf << (4 * (idx - FRAG_RESULT_DATA0));
if (idx == FRAG_RESULT_DATA0)
info->ps.color0_written = write_mask;
}
break;
default:
break;
@@ -563,6 +567,10 @@ gather_shader_info_fs(const nir_shader *nir, const struct radv_pipeline_key *pip
info->ps.has_epilog = pipeline_key->ps.has_epilog;
info->ps.writes_mrt0_alpha =
(pipeline_key->ps.alpha_to_coverage_via_mrtz && (info->ps.color0_written & 0x8)) &&
(info->ps.writes_z || info->ps.writes_stencil || info->ps.writes_sample_mask);
nir_foreach_shader_in_variable(var, nir) {
unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
int idx = var->data.location;