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radeonsi/sqtt: don't store the offsets in the pipeline

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We can pass them to si_sqtt_register_pipeline / si_sqtt_add_code_object
directly instead.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31171>
This commit is contained in:
Pierre-Eric Pelloux-Prayer
2024-09-13 17:08:32 +02:00
committed by Marge Bot
parent bda9e1f856
commit 3ab34c5ffe
4 changed files with 13 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/radeonsi/si_compute.c
+1 -1
View File
@@ -339,7 +339,7 @@ static void si_bind_compute_state(struct pipe_context *ctx, void *state)
pipeline.code_hash = pipeline_code_hash;
pipeline.bo = program->shader.bo;
si_sqtt_register_pipeline(sctx, &pipeline, true);
si_sqtt_register_pipeline(sctx, &pipeline, NULL);
}
si_sqtt_describe_pipeline_bind(sctx, pipeline_code_hash, 1);
src/gallium/drivers/radeonsi/si_pipe.h
+2 -2
View File
@@ -883,7 +883,6 @@ struct si_sqtt_fake_pipeline {
struct si_pm4_state pm4; /* base class */
uint64_t code_hash;
struct si_resource *bo;
uint32_t offset[SI_NUM_GRAPHICS_SHADERS];
};
struct si_small_prim_cull_info {
@@ -1720,7 +1719,8 @@ void si_sqtt_write_event_marker(struct si_context* sctx, struct radeon_cmdbuf *r
uint32_t vertex_offset_user_data,
uint32_t instance_offset_user_data,
uint32_t draw_index_user_data);
bool si_sqtt_register_pipeline(struct si_context* sctx, struct si_sqtt_fake_pipeline *pipeline, bool is_compute);
bool si_sqtt_register_pipeline(struct si_context* sctx, struct si_sqtt_fake_pipeline *pipeline,
uint32_t *gfx_sh_offsets);
bool si_sqtt_pipeline_is_registered(struct ac_sqtt *sqtt,
uint64_t pipeline_hash);
void si_sqtt_describe_pipeline_bind(struct si_context* sctx, uint64_t pipeline_hash, int bind_point);
src/gallium/drivers/radeonsi/si_sqtt.c
+6 -4
View File
@@ -732,10 +732,11 @@ si_sqtt_pipe_to_rgp_shader_stage(union si_shader_key *key, enum pipe_shader_type
static bool
si_sqtt_add_code_object(struct si_context *sctx,
struct si_sqtt_fake_pipeline *pipeline,
bool is_compute)
uint32_t *gfx_sh_offsets)
{
struct rgp_code_object *code_object = &sctx->sqtt->rgp_code_object;
struct rgp_code_object_record *record;
bool is_compute = gfx_sh_offsets == NULL;
record = calloc(1, sizeof(struct rgp_code_object_record));
if (!record)
@@ -771,7 +772,7 @@ si_sqtt_add_code_object(struct si_context *sctx,
}
memcpy(code, shader->binary.uploaded_code, shader->binary.uploaded_code_size);
uint64_t va = pipeline->bo->gpu_address + pipeline->offset[i];
uint64_t va = pipeline->bo->gpu_address + (is_compute ? 0 : gfx_sh_offsets[i]);
unsigned lds_increment = sctx->gfx_level >= GFX11 && i == MESA_SHADER_FRAGMENT ?
1024 : sctx->screen->info.lds_encode_granularity;
@@ -802,7 +803,8 @@ si_sqtt_add_code_object(struct si_context *sctx,
return true;
}
bool si_sqtt_register_pipeline(struct si_context *sctx, struct si_sqtt_fake_pipeline *pipeline, bool is_compute)
bool si_sqtt_register_pipeline(struct si_context *sctx, struct si_sqtt_fake_pipeline *pipeline,
uint32_t *gfx_sh_offsets)
{
assert(!si_sqtt_pipeline_is_registered(sctx->sqtt, pipeline->code_hash));
@@ -815,7 +817,7 @@ bool si_sqtt_register_pipeline(struct si_context *sctx, struct si_sqtt_fake_pipe
if (!result)
return false;
return si_sqtt_add_code_object(sctx, pipeline, is_compute);
return si_sqtt_add_code_object(sctx, pipeline, gfx_sh_offsets);
}
void si_sqtt_describe_pipeline_bind(struct si_context *sctx,
src/gallium/drivers/radeonsi/si_state_draw.cpp
+4 -2
View File
@@ -367,13 +367,15 @@ static bool si_update_shaders(struct si_context *sctx)
/* Re-upload all gfx shaders and init PM4. */
si_pm4_clear_state(&pipeline->pm4, sctx->screen, false);
uint32_t gfx_sh_offsets[SI_NUM_GRAPHICS_SHADERS] = { 0 };
for (int i = 0; i < SI_NUM_GRAPHICS_SHADERS; i++) {
struct si_shader *shader = sctx->shaders[i].current;
if (sctx->shaders[i].cso && shader) {
si_resource_reference(&shader->bo, bo);
int size = si_shader_binary_upload_at(sctx->screen, shader, scratch_va, offset);
pipeline->offset[i] = offset;
gfx_sh_offsets[i] = offset;
offset += align(size, 256);
struct si_pm4_state *pm4 = &shader->pm4;
@@ -389,7 +391,7 @@ static bool si_update_shaders(struct si_context *sctx)
_mesa_hash_table_u64_insert(sctx->sqtt->pipeline_bos,
pipeline_code_hash, pipeline);
si_sqtt_register_pipeline(sctx, pipeline, false);
si_sqtt_register_pipeline(sctx, pipeline, gfx_sh_offsets);
} else {
if (bo)
si_resource_reference(&bo, NULL);