AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

gallium/pb_buffer: define pb_buffer_lean without vtbl, inherit it by pb_buffer

Browse Source 
amdgpu doesn't need vtbl.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26643>
This commit is contained in:
Marek Olšák
2023-12-09 15:13:38 -05:00
committed by Marge Bot
parent eb19f0daa3
commit 39c1311766
37 changed files with 312 additions and 303 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/auxiliary/pipebuffer/pb_buffer.h
+17 -8
View File
@@ -106,9 +106,9 @@ typedef uint64_t pb_size;
/**
* Base class for all pb_* buffers.
* Base class for all pb_* buffers without the vtbl pointer.
*/
struct pb_buffer
struct pb_buffer_lean
{
struct pipe_reference reference;
@@ -129,6 +129,15 @@ struct pb_buffer
uint16_t usage;
pb_size size;
};
/**
* Base class for all pb_* buffers with the vtbl pointer.
*/
struct pb_buffer
{
struct pb_buffer_lean base;
/**
* Pointer to the virtual function table.
@@ -191,7 +200,7 @@ pb_map(struct pb_buffer *buf, enum pb_usage_flags flags, void *flush_ctx)
assert(buf);
if (!buf)
return NULL;
assert(pipe_is_referenced(&buf->reference));
assert(pipe_is_referenced(&buf->base.reference));
return buf->vtbl->map(buf, flags, flush_ctx);
}
@@ -202,7 +211,7 @@ pb_unmap(struct pb_buffer *buf)
assert(buf);
if (!buf)
return;
assert(pipe_is_referenced(&buf->reference));
assert(pipe_is_referenced(&buf->base.reference));
buf->vtbl->unmap(buf);
}
@@ -218,11 +227,11 @@ pb_get_base_buffer(struct pb_buffer *buf,
offset = NULL;
return;
}
assert(pipe_is_referenced(&buf->reference));
assert(pipe_is_referenced(&buf->base.reference));
assert(buf->vtbl->get_base_buffer);
buf->vtbl->get_base_buffer(buf, base_buf, offset);
assert(*base_buf);
assert(*offset < (*base_buf)->size);
assert(*offset < (*base_buf)->base.size);
}
@@ -270,7 +279,7 @@ pb_reference(struct pb_buffer **dst,
{
struct pb_buffer *old = *dst;
if (pipe_reference(&(*dst)->reference, &src->reference))
if (pipe_reference(&(*dst)->base.reference, &src->base.reference))
pb_destroy(NULL, old);
*dst = src;
}
@@ -282,7 +291,7 @@ pb_reference_with_winsys(void *winsys,
{
struct pb_buffer *old = *dst;
if (pipe_reference(&(*dst)->reference, &src->reference))
if (pipe_reference(&(*dst)->base.reference, &src->base.reference))
pb_destroy(winsys, old);
*dst = src;
}
src/gallium/auxiliary/pipebuffer/pb_buffer_fenced.c
+16 -16
View File
@@ -211,8 +211,8 @@ fenced_manager_dump_locked(struct fenced_manager *fenced_mgr)
assert(!fenced_buf->fence);
debug_printf("%10p %"PRIu64" %8u %7s\n",
(void *) fenced_buf,
fenced_buf->base.size,
p_atomic_read(&fenced_buf->base.reference.count),
fenced_buf->base.base.size,
p_atomic_read(&fenced_buf->base.base.reference.count),
fenced_buf->buffer ? "gpu" : (fenced_buf->data ? "cpu" : "none"));
curr = next;
next = curr->next;
@@ -227,8 +227,8 @@ fenced_manager_dump_locked(struct fenced_manager *fenced_mgr)
signaled = ops->fence_signalled(ops, fenced_buf->fence, 0);
debug_printf("%10p %"PRIu64" %8u %7s %10p %s\n",
(void *) fenced_buf,
fenced_buf->base.size,
p_atomic_read(&fenced_buf->base.reference.count),
fenced_buf->base.base.size,
p_atomic_read(&fenced_buf->base.base.reference.count),
"gpu",
(void *) fenced_buf->fence,
signaled == 0 ? "y" : "n");
@@ -245,7 +245,7 @@ static inline void
fenced_buffer_destroy_locked(struct fenced_manager *fenced_mgr,
struct fenced_buffer *fenced_buf)
{
assert(!pipe_is_referenced(&fenced_buf->base.reference));
assert(!pipe_is_referenced(&fenced_buf->base.base.reference));
assert(!fenced_buf->fence);
assert(fenced_buf->head.prev);
@@ -270,11 +270,11 @@ static inline void
fenced_buffer_add_locked(struct fenced_manager *fenced_mgr,
struct fenced_buffer *fenced_buf)
{
assert(pipe_is_referenced(&fenced_buf->base.reference));
assert(pipe_is_referenced(&fenced_buf->base.base.reference));
assert(fenced_buf->flags & PB_USAGE_GPU_READ_WRITE);
assert(fenced_buf->fence);
p_atomic_inc(&fenced_buf->base.reference.count);
p_atomic_inc(&fenced_buf->base.base.reference.count);
list_del(&fenced_buf->head);
assert(fenced_mgr->num_unfenced);
@@ -312,7 +312,7 @@ fenced_buffer_remove_locked(struct fenced_manager *fenced_mgr,
list_addtail(&fenced_buf->head, &fenced_mgr->unfenced);
++fenced_mgr->num_unfenced;
if (p_atomic_dec_zero(&fenced_buf->base.reference.count)) {
if (p_atomic_dec_zero(&fenced_buf->base.base.reference.count)) {
fenced_buffer_destroy_locked(fenced_mgr, fenced_buf);
return true;
}
@@ -338,7 +338,7 @@ fenced_buffer_finish_locked(struct fenced_manager *fenced_mgr,
debug_warning("waiting for GPU");
#endif
assert(pipe_is_referenced(&fenced_buf->base.reference));
assert(pipe_is_referenced(&fenced_buf->base.base.reference));
assert(fenced_buf->fence);
if (fenced_buf->fence) {
@@ -354,7 +354,7 @@ fenced_buffer_finish_locked(struct fenced_manager *fenced_mgr,
mtx_lock(&fenced_mgr->mutex);
assert(pipe_is_referenced(&fenced_buf->base.reference));
assert(pipe_is_referenced(&fenced_buf->base.base.reference));
/* Only proceed if the fence object didn't change in the meanwhile.
* Otherwise assume the work has been already carried out by another
@@ -650,7 +650,7 @@ fenced_buffer_destroy(void *winsys, struct pb_buffer *buf)
struct fenced_buffer *fenced_buf = fenced_buffer(buf);
struct fenced_manager *fenced_mgr = fenced_buf->mgr;
assert(!pipe_is_referenced(&fenced_buf->base.reference));
assert(!pipe_is_referenced(&fenced_buf->base.base.reference));
mtx_lock(&fenced_mgr->mutex);
@@ -818,7 +818,7 @@ fenced_buffer_fence(struct pb_buffer *buf,
mtx_lock(&fenced_mgr->mutex);
assert(pipe_is_referenced(&fenced_buf->base.reference));
assert(pipe_is_referenced(&fenced_buf->base.base.reference));
assert(fenced_buf->buffer);
if (fence != fenced_buf->fence) {
@@ -907,10 +907,10 @@ fenced_bufmgr_create_buffer(struct pb_manager *mgr,
if (!fenced_buf)
goto no_buffer;
pipe_reference_init(&fenced_buf->base.reference, 1);
fenced_buf->base.alignment_log2 = util_logbase2(desc->alignment);
fenced_buf->base.usage = desc->usage;
fenced_buf->base.size = size;
pipe_reference_init(&fenced_buf->base.base.reference, 1);
fenced_buf->base.base.alignment_log2 = util_logbase2(desc->alignment);
fenced_buf->base.base.usage = desc->usage;
fenced_buf->base.base.size = size;
fenced_buf->size = size;
fenced_buf->desc = *desc;
src/gallium/auxiliary/pipebuffer/pb_bufmgr_cache.c
+8 -8
View File
@@ -98,7 +98,7 @@ _pb_cache_buffer_destroy(void *winsys, struct pb_buffer *pb_buf)
{
struct pb_cache_buffer *buf = pb_cache_buffer(pb_buf);
assert(!pipe_is_referenced(&buf->base.reference));
assert(!pipe_is_referenced(&buf->base.base.reference));
pb_reference(&buf->buffer, NULL);
FREE(buf);
}
@@ -233,14 +233,14 @@ pb_cache_manager_create_buffer(struct pb_manager *_mgr,
return NULL;
}
assert(pipe_is_referenced(&buf->buffer->reference));
assert(pb_check_alignment(desc->alignment, 1u << buf->buffer->alignment_log2));
assert(buf->buffer->size >= aligned_size);
assert(pipe_is_referenced(&buf->buffer->base.reference));
assert(pb_check_alignment(desc->alignment, 1u << buf->buffer->base.alignment_log2));
assert(buf->buffer->base.size >= aligned_size);
pipe_reference_init(&buf->base.reference, 1);
buf->base.alignment_log2 = buf->buffer->alignment_log2;
buf->base.usage = buf->buffer->usage;
buf->base.size = buf->buffer->size;
pipe_reference_init(&buf->base.base.reference, 1);
buf->base.base.alignment_log2 = buf->buffer->base.alignment_log2;
buf->base.base.usage = buf->buffer->base.usage;
buf->base.base.size = buf->buffer->base.size;
buf->base.vtbl = &pb_cache_buffer_vtbl;
buf->mgr = mgr;
src/gallium/auxiliary/pipebuffer/pb_bufmgr_debug.c
+15 -15
View File
@@ -162,7 +162,7 @@ pb_debug_buffer_fill(struct pb_debug_buffer *buf)
assert(map);
if (map) {
fill_random_pattern(map, buf->underflow_size);
fill_random_pattern(map + buf->underflow_size + buf->base.size,
fill_random_pattern(map + buf->underflow_size + buf->base.base.size,
buf->overflow_size);
pb_unmap(buf->buffer);
}
@@ -196,12 +196,12 @@ pb_debug_buffer_check(struct pb_debug_buffer *buf)
buf->underflow_size - max_ofs);
}
overflow = !check_random_pattern(map + buf->underflow_size + buf->base.size,
overflow = !check_random_pattern(map + buf->underflow_size + buf->base.base.size,
buf->overflow_size,
&min_ofs, &max_ofs);
if(overflow) {
debug_printf("buffer overflow (size %"PRIu64" plus offset %"PRIu64" to %"PRIu64"%s bytes) detected\n",
buf->base.size,
buf->base.base.size,
min_ofs,
max_ofs,
max_ofs == buf->overflow_size - 1 ? "+" : "");
@@ -217,7 +217,7 @@ pb_debug_buffer_check(struct pb_debug_buffer *buf)
if(underflow)
fill_random_pattern(map, buf->underflow_size);
if(overflow)
fill_random_pattern(map + buf->underflow_size + buf->base.size,
fill_random_pattern(map + buf->underflow_size + buf->base.base.size,
buf->overflow_size);
pb_unmap(buf->buffer);
@@ -231,7 +231,7 @@ pb_debug_buffer_destroy(void *winsys, struct pb_buffer *_buf)
struct pb_debug_buffer *buf = pb_debug_buffer(_buf);
struct pb_debug_manager *mgr = buf->mgr;
assert(!pipe_is_referenced(&buf->base.reference));
assert(!pipe_is_referenced(&buf->base.base.reference));
pb_debug_buffer_check(buf);
@@ -351,7 +351,7 @@ pb_debug_manager_dump_locked(struct pb_debug_manager *mgr)
buf = list_entry(curr, struct pb_debug_buffer, head);
debug_printf("buffer = %p\n", (void *) buf);
debug_printf(" .size = 0x%"PRIx64"\n", buf->base.size);
debug_printf(" .size = 0x%"PRIx64"\n", buf->base.base.size);
debug_backtrace_dump(buf->create_backtrace, PB_DEBUG_CREATE_BACKTRACE);
curr = next;
@@ -398,21 +398,21 @@ pb_debug_manager_create_buffer(struct pb_manager *_mgr,
return NULL;
}
assert(pipe_is_referenced(&buf->buffer->reference));
assert(pb_check_alignment(real_desc.alignment, 1u << buf->buffer->alignment_log2));
assert(pb_check_usage(real_desc.usage, buf->buffer->usage));
assert(buf->buffer->size >= real_size);
assert(pipe_is_referenced(&buf->buffer->base.reference));
assert(pb_check_alignment(real_desc.alignment, 1u << buf->buffer->base.alignment_log2));
assert(pb_check_usage(real_desc.usage, buf->buffer->base.usage));
assert(buf->buffer->base.size >= real_size);
pipe_reference_init(&buf->base.reference, 1);
buf->base.alignment_log2 = util_logbase2(desc->alignment);
buf->base.usage = desc->usage;
buf->base.size = size;
pipe_reference_init(&buf->base.base.reference, 1);
buf->base.base.alignment_log2 = util_logbase2(desc->alignment);
buf->base.base.usage = desc->usage;
buf->base.base.size = size;
buf->base.vtbl = &pb_debug_buffer_vtbl;
buf->mgr = mgr;
buf->underflow_size = mgr->underflow_size;
buf->overflow_size = buf->buffer->size - buf->underflow_size - size;
buf->overflow_size = buf->buffer->base.size - buf->underflow_size - size;
debug_backtrace_capture(buf->create_backtrace, 1, PB_DEBUG_CREATE_BACKTRACE);
src/gallium/auxiliary/pipebuffer/pb_bufmgr_mm.c
+5 -5
View File
@@ -97,7 +97,7 @@ mm_buffer_destroy(void *winsys, struct pb_buffer *buf)
struct mm_buffer *mm_buf = mm_buffer(buf);
struct mm_pb_manager *mm = mm_buf->mgr;
assert(!pipe_is_referenced(&mm_buf->base.reference));
assert(!pipe_is_referenced(&mm_buf->base.base.reference));
mtx_lock(&mm->mutex);
u_mmFreeMem(mm_buf->block);
@@ -192,10 +192,10 @@ mm_bufmgr_create_buffer(struct pb_manager *mgr,
return NULL;
}
pipe_reference_init(&mm_buf->base.reference, 1);
mm_buf->base.alignment_log2 = util_logbase2(desc->alignment);
mm_buf->base.usage = desc->usage;
mm_buf->base.size = size;
pipe_reference_init(&mm_buf->base.base.reference, 1);
mm_buf->base.base.alignment_log2 = util_logbase2(desc->alignment);
mm_buf->base.base.usage = desc->usage;
mm_buf->base.base.size = size;
mm_buf->base.vtbl = &mm_buffer_vtbl;
src/gallium/auxiliary/pipebuffer/pb_bufmgr_slab.c
+9 -9
View File
@@ -196,7 +196,7 @@ pb_slab_buffer_destroy(void *winsys, struct pb_buffer *_buf)
mtx_lock(&mgr->mutex);
assert(!pipe_is_referenced(&buf->base.reference));
assert(!pipe_is_referenced(&buf->base.base.reference));
buf->mapCount = 0;
@@ -321,7 +321,7 @@ pb_slab_create(struct pb_slab_manager *mgr)
goto out_err1;
}
numBuffers = slab->bo->size / mgr->bufSize;
numBuffers = slab->bo->base.size / mgr->bufSize;
slab->buffers = CALLOC(numBuffers, sizeof(*slab->buffers));
if (!slab->buffers) {
@@ -337,10 +337,10 @@ pb_slab_create(struct pb_slab_manager *mgr)
buf = slab->buffers;
for (i=0; i < numBuffers; ++i) {
pipe_reference_init(&buf->base.reference, 0);
buf->base.size = mgr->bufSize;
buf->base.alignment_log2 = 0;
buf->base.usage = 0;
pipe_reference_init(&buf->base.base.reference, 0);
buf->base.base.size = mgr->bufSize;
buf->base.base.alignment_log2 = 0;
buf->base.base.usage = 0;
buf->base.vtbl = &pb_slab_buffer_vtbl;
buf->slab = slab;
buf->start = i* mgr->bufSize;
@@ -415,9 +415,9 @@ pb_slab_manager_create_buffer(struct pb_manager *_mgr,
mtx_unlock(&mgr->mutex);
buf = list_entry(list, struct pb_slab_buffer, head);
pipe_reference_init(&buf->base.reference, 1);
buf->base.alignment_log2 = util_logbase2(desc->alignment);
buf->base.usage = desc->usage;
pipe_reference_init(&buf->base.base.reference, 1);
buf->base.base.alignment_log2 = util_logbase2(desc->alignment);
buf->base.base.usage = desc->usage;
return &buf->base;
}
src/gallium/auxiliary/pipebuffer/pb_cache.c
+11 -11
View File
@@ -62,12 +62,12 @@ destroy_buffer_locked(struct pb_cache_entry *entry)
struct pb_cache *mgr = entry->mgr;
struct pb_buffer *buf = entry->buffer;
assert(!pipe_is_referenced(&buf->reference));
assert(!pipe_is_referenced(&buf->base.reference));
if (list_is_linked(&entry->head)) {
list_del(&entry->head);
assert(mgr->num_buffers);
--mgr->num_buffers;
mgr->cache_size -= buf->size;
mgr->cache_size -= buf->base.size;
}
mgr->destroy_buffer(mgr->winsys, buf);
}
@@ -111,7 +111,7 @@ pb_cache_add_buffer(struct pb_cache_entry *entry)
unsigned i;
simple_mtx_lock(&mgr->mutex);
assert(!pipe_is_referenced(&buf->reference));
assert(!pipe_is_referenced(&buf->base.reference));
unsigned current_time_ms = time_get_ms(mgr);
@@ -119,7 +119,7 @@ pb_cache_add_buffer(struct pb_cache_entry *entry)
release_expired_buffers_locked(&mgr->buckets[i], current_time_ms);
/* Directly release any buffer that exceeds the limit. */
if (mgr->cache_size + buf->size > mgr->max_cache_size) {
if (mgr->cache_size + buf->base.size > mgr->max_cache_size) {
mgr->destroy_buffer(mgr->winsys, buf);
simple_mtx_unlock(&mgr->mutex);
return;
@@ -128,7 +128,7 @@ pb_cache_add_buffer(struct pb_cache_entry *entry)
entry->start_ms = time_get_ms(mgr);
list_addtail(&entry->head, cache);
++mgr->num_buffers;
mgr->cache_size += buf->size;
mgr->cache_size += buf->base.size;
simple_mtx_unlock(&mgr->mutex);
}
@@ -144,18 +144,18 @@ pb_cache_is_buffer_compat(struct pb_cache_entry *entry,
struct pb_cache *mgr = entry->mgr;
struct pb_buffer *buf = entry->buffer;
if (!pb_check_usage(usage, buf->usage))
if (!pb_check_usage(usage, buf->base.usage))
return 0;
/* be lenient with size */
if (buf->size < size ||
buf->size > (unsigned) (mgr->size_factor * size))
if (buf->base.size < size ||
buf->base.size > (unsigned) (mgr->size_factor * size))
return 0;
if (usage & mgr->bypass_usage)
return 0;
if (!pb_check_alignment(alignment, 1u << buf->alignment_log2))
if (!pb_check_alignment(alignment, 1u << buf->base.alignment_log2))
return 0;
return mgr->can_reclaim(mgr->winsys, buf) ? 1 : -1;
@@ -228,12 +228,12 @@ pb_cache_reclaim_buffer(struct pb_cache *mgr, pb_size size,
if (entry) {
struct pb_buffer *buf = entry->buffer;
mgr->cache_size -= buf->size;
mgr->cache_size -= buf->base.size;
list_del(&entry->head);
--mgr->num_buffers;
simple_mtx_unlock(&mgr->mutex);
/* Increase refcount */
pipe_reference_init(&buf->reference, 1);
pipe_reference_init(&buf->base.reference, 1);
return buf;
}
src/gallium/drivers/d3d12/d3d12_bufmgr.cpp
+5 -5
View File
@@ -64,7 +64,7 @@ describe_suballoc_bo(char *buf, struct d3d12_bo *ptr)
d3d12_bo *base = d3d12_bo_get_base(ptr, &offset);
describe_direct_bo(res, base);
sprintf(buf, "d3d12_bo<suballoc<%s>,0x%x,0x%x>", res,
(unsigned)ptr->buffer->size, (unsigned)offset);
(unsigned)ptr->buffer->base.size, (unsigned)offset);
}
void
@@ -332,11 +332,11 @@ d3d12_bufmgr_create_buffer(struct pb_manager *pmgr,
if (!buf)
return NULL;
pipe_reference_init(&buf->base.reference, 1);
buf->base.alignment_log2 = util_logbase2(pb_desc->alignment);
buf->base.usage = pb_desc->usage;
pipe_reference_init(&buf->base.base.reference, 1);
buf->base.base.alignment_log2 = util_logbase2(pb_desc->alignment);
buf->base.base.usage = pb_desc->usage;
buf->base.vtbl = &d3d12_buffer_vtbl;
buf->base.size = size;
buf->base.base.size = size;
buf->range.Begin = 0;
buf->range.End = size;
src/gallium/drivers/d3d12/d3d12_bufmgr.h
+1 -1
View File
@@ -106,7 +106,7 @@ static inline uint64_t
d3d12_bo_get_size(struct d3d12_bo *bo)
{
if (bo->buffer)
return bo->buffer->size;
return bo->buffer->base.size;
else
return GetDesc(bo->res).Width;
}
src/gallium/drivers/r300/r300_emit.c
+2 -2
View File
@@ -770,8 +770,8 @@ void r300_emit_query_end(struct r300_context* r300)
query->num_results += query->num_pipes;
/* XXX grab all the results and reset the counter. */
if (query->num_results >= query->buf->size / 4 - 4) {
query->num_results = (query->buf->size / 4) / 2;
if (query->num_results >= query->buf->base.size / 4 - 4) {
query->num_results = (query->buf->base.size / 4) / 2;
fprintf(stderr, "r300: Rewinding OQBO...\n");
}
}
src/gallium/drivers/r300/r300_render.c
+2 -2
View File
@@ -950,7 +950,7 @@ static bool r300_render_allocate_vertices(struct vbuf_render* render,
DBG(r300, DBG_DRAW, "r300: render_allocate_vertices (size: %d)\n", size);
if (!r300->vbo || size + r300->draw_vbo_offset > r300->vbo->size) {
if (!r300->vbo || size + r300->draw_vbo_offset > r300->vbo->base.size) {
radeon_bo_reference(r300->rws, &r300->vbo, NULL);
r300->vbo = NULL;
r300render->vbo_ptr = NULL;
@@ -1056,7 +1056,7 @@ static void r300_render_draw_elements(struct vbuf_render* render,
{
struct r300_render* r300render = r300_render(render);
struct r300_context* r300 = r300render->r300;
unsigned max_index = (r300->vbo->size - r300->draw_vbo_offset) /
unsigned max_index = (r300->vbo->base.size - r300->draw_vbo_offset) /
(r300render->r300->vertex_info.size * 4) - 1;
struct pipe_resource *index_buffer = NULL;
unsigned index_buffer_offset;
src/gallium/drivers/r300/r300_texture_desc.c
+3 -3
View File
@@ -606,17 +606,17 @@ void r300_texture_desc_init(struct r300_screen *rscreen,
r300_setup_miptree(rscreen, tex, true);
/* If the required buffer size is larger than the given max size,
* try again without the alignment for the CBZB clear. */
if (tex->buf && tex->tex.size_in_bytes > tex->buf->size) {
if (tex->buf && tex->tex.size_in_bytes > tex->buf->base.size) {
r300_setup_miptree(rscreen, tex, false);
/* Make sure the buffer we got is large enough. */
if (tex->tex.size_in_bytes > tex->buf->size) {
if (tex->tex.size_in_bytes > tex->buf->base.size) {
fprintf(stderr,
"r300: I got a pre-allocated buffer to use it as a texture "
"storage, but the buffer is too small. I'll use the buffer "
"anyway, because I can't crash here, but it's dangerous. "
"This can be a DDX bug. Got: %"PRIu64"B, Need: %uB, Info:\n",
tex->buf->size, tex->tex.size_in_bytes);
tex->buf->base.size, tex->tex.size_in_bytes);
r300_tex_print_info(tex, "texture_desc_init");
/* Oops, what now. Apps will break if we fail this,
* so just pretend everything's okay. */
src/gallium/drivers/r600/r600_buffer_common.c
+2 -2
View File
@@ -195,8 +195,8 @@ bool r600_alloc_resource(struct r600_common_screen *rscreen,
/* Print debug information. */
if (rscreen->debug_flags & DBG_VM && res->b.b.target == PIPE_BUFFER) {
fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Buffer %"PRIu64" bytes\n",
res->gpu_address, res->gpu_address + res->buf->size,
res->buf->size);
res->gpu_address, res->gpu_address + res->buf->base.size,
res->buf->base.size);
}
return true;
}
src/gallium/drivers/r600/r600_state.c
+2 -2
View File
@@ -990,7 +990,7 @@ static void r600_init_color_surface(struct r600_context *rctx,
/* CMASK. */
if (!rctx->dummy_cmask ||
rctx->dummy_cmask->b.b.width0 < cmask.size ||
(1 << rctx->dummy_cmask->buf->alignment_log2) % cmask.alignment != 0) {
(1 << rctx->dummy_cmask->buf->base.alignment_log2) % cmask.alignment != 0) {
struct pipe_transfer *transfer;
void *ptr;
@@ -1015,7 +1015,7 @@ static void r600_init_color_surface(struct r600_context *rctx,
/* FMASK. */
if (!rctx->dummy_fmask ||
rctx->dummy_fmask->b.b.width0 < fmask.size ||
(1 << rctx->dummy_fmask->buf->alignment_log2) % fmask.alignment != 0) {
(1 << rctx->dummy_fmask->buf->base.alignment_log2) % fmask.alignment != 0) {
r600_resource_reference(&rctx->dummy_fmask, NULL);
rctx->dummy_fmask = (struct r600_resource*)
r600_aligned_buffer_create(&rscreen->b.b, 0,
src/gallium/drivers/r600/r600_texture.c
+6 -6
View File
@@ -973,13 +973,13 @@ r600_texture_create_object(struct pipe_screen *screen,
} else {
resource->buf = buf;
resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
resource->bo_size = buf->size;
resource->bo_alignment = 1 << buf->alignment_log2;
resource->bo_size = buf->base.size;
resource->bo_alignment = 1 << buf->base.alignment_log2;
resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
if (resource->domains & RADEON_DOMAIN_VRAM)
resource->vram_usage = buf->size;
resource->vram_usage = buf->base.size;
else if (resource->domains & RADEON_DOMAIN_GTT)
resource->gart_usage = buf->size;
resource->gart_usage = buf->base.size;
}
if (rtex->cmask.size) {
@@ -1004,7 +1004,7 @@ r600_texture_create_object(struct pipe_screen *screen,
if (rscreen->debug_flags & DBG_VM) {
fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
rtex->resource.gpu_address,
rtex->resource.gpu_address + rtex->resource.buf->size,
rtex->resource.gpu_address + rtex->resource.buf->base.size,
base->width0, base->height0, util_num_layers(base, 0), base->last_level+1,
base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
}
@@ -1486,7 +1486,7 @@ void r600_texture_transfer_unmap(struct pipe_context *ctx,
}
if (rtransfer->staging) {
rctx->num_alloc_tex_transfer_bytes += rtransfer->staging->buf->size;
rctx->num_alloc_tex_transfer_bytes += rtransfer->staging->buf->base.size;
r600_resource_reference(&rtransfer->staging, NULL);
}
src/gallium/drivers/r600/radeon_uvd.c
+2 -2
View File
@@ -887,7 +887,7 @@ static void ruvd_decode_bitstream(struct pipe_video_codec *decoder,
if (format == PIPE_VIDEO_FORMAT_JPEG)
new_size += 2; /* save for EOI */
if (new_size > buf->res->buf->size) {
if (new_size > buf->res->buf->base.size) {
dec->ws->buffer_unmap(dec->ws, buf->res->buf);
dec->bs_ptr = NULL;
if (!rvid_resize_buffer(dec->screen, &dec->cs, buf, new_size)) {
@@ -960,7 +960,7 @@ static void ruvd_end_frame(struct pipe_video_codec *decoder,
}
if (dec->dpb.res)
dec->msg->body.decode.dpb_size = dec->dpb.res->buf->size;
dec->msg->body.decode.dpb_size = dec->dpb.res->buf->base.size;
dec->msg->body.decode.bsd_size = bs_size;
dec->msg->body.decode.db_pitch = align(dec->base.width, get_db_pitch_alignment(dec));
src/gallium/drivers/r600/radeon_video.c
+5 -5
View File
@@ -90,7 +90,7 @@ bool rvid_resize_buffer(struct pipe_screen *screen, struct radeon_cmdbuf *cs,
{
struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
struct radeon_winsys* ws = rscreen->ws;
unsigned bytes = MIN2(new_buf->res->buf->size, new_size);
unsigned bytes = MIN2(new_buf->res->buf->base.size, new_size);
struct rvid_buffer old_buf = *new_buf;
void *src = NULL, *dst = NULL;
@@ -132,7 +132,7 @@ void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer)
struct r600_common_context *rctx = (struct r600_common_context*)context;
rctx->dma_clear_buffer(context, &buffer->res->b.b, 0,
buffer->res->buf->size, 0);
buffer->res->buf->base.size, 0);
context->flush(context, NULL, 0);
}
@@ -189,9 +189,9 @@ void rvid_join_surfaces(struct r600_common_context *rctx,
if (!buffers[i] || !*buffers[i])
continue;
size = align(size, 1 << (*buffers[i])->alignment_log2);
size += (*buffers[i])->size;
alignment = MAX2(alignment, 1 << (*buffers[i])->alignment_log2);
size = align(size, 1 << (*buffers[i])->base.alignment_log2);
size += (*buffers[i])->base.size;
alignment = MAX2(alignment, 1 << (*buffers[i])->base.alignment_log2);
}
if (!size)
src/gallium/drivers/radeonsi/radeon_uvd.c
+4 -4
View File
@@ -1046,7 +1046,7 @@ static void ruvd_decode_bitstream(struct pipe_video_codec *decoder,
struct rvid_buffer *buf = &dec->bs_buffers[dec->cur_buffer];
unsigned new_size = dec->bs_size + sizes[i];
if (new_size > buf->res->buf->size) {
if (new_size > buf->res->buf->base.size) {
dec->ws->buffer_unmap(dec->ws, buf->res->buf);
if (!si_vid_resize_buffer(dec->screen, &dec->cs, buf, new_size, NULL)) {
RVID_ERR("Can't resize bitstream buffer!");
@@ -1110,13 +1110,13 @@ static void ruvd_end_frame(struct pipe_video_codec *decoder, struct pipe_video_b
}
if (dec->dpb.res)
dec->msg->body.decode.dpb_size = dec->dpb.res->buf->size;
dec->msg->body.decode.dpb_size = dec->dpb.res->buf->base.size;
dec->msg->body.decode.bsd_size = bs_size;
dec->msg->body.decode.db_pitch = align(dec->base.width, get_db_pitch_alignment(dec));
if (dec->stream_type == RUVD_CODEC_H264_PERF &&
((struct si_screen *)dec->screen)->info.family >= CHIP_POLARIS10)
dec->msg->body.decode.dpb_reserved = dec->ctx.res->buf->size;
dec->msg->body.decode.dpb_reserved = dec->ctx.res->buf->base.size;
dt = dec->set_dtb(dec->msg, (struct vl_video_buffer *)target);
if (((struct si_screen *)dec->screen)->info.family >= CHIP_STONEY)
@@ -1144,7 +1144,7 @@ static void ruvd_end_frame(struct pipe_video_codec *decoder, struct pipe_video_b
}
if (dec->ctx.res)
dec->msg->body.decode.dpb_reserved = dec->ctx.res->buf->size;
dec->msg->body.decode.dpb_reserved = dec->ctx.res->buf->base.size;
break;
case PIPE_VIDEO_FORMAT_VC1:
src/gallium/drivers/radeonsi/radeon_vce_50.c
+1 -1
View File
@@ -79,7 +79,7 @@ static void encode(struct rvce_encoder *enc)
if (enc->dual_pipe) {
unsigned aux_offset =
enc->cpb.res->buf->size - RVCE_MAX_AUX_BUFFER_NUM * RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2;
enc->cpb.res->buf->base.size - RVCE_MAX_AUX_BUFFER_NUM * RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2;
RVCE_BEGIN(0x05000002); // auxiliary buffer
for (i = 0; i < 8; ++i) {
RVCE_CS(aux_offset);
src/gallium/drivers/radeonsi/radeon_vce_52.c
+1 -1
View File
@@ -226,7 +226,7 @@ static void encode(struct rvce_encoder *enc)
if (enc->dual_pipe) {
unsigned aux_offset =
enc->cpb.res->buf->size - RVCE_MAX_AUX_BUFFER_NUM * RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2;
enc->cpb.res->buf->base.size - RVCE_MAX_AUX_BUFFER_NUM * RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2;
RVCE_BEGIN(0x05000002); // auxiliary buffer
for (i = 0; i < 8; ++i) {
RVCE_CS(aux_offset);
src/gallium/drivers/radeonsi/radeon_vcn_dec.c
+6 -6
View File
@@ -2164,14 +2164,14 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
luma = (struct si_texture *)((struct vl_video_buffer *)out_surf)->resources[0];
chroma = (struct si_texture *)((struct vl_video_buffer *)out_surf)->resources[1];
decode->dpb_size = (dec->dpb_type != DPB_DYNAMIC_TIER_2) ? dec->dpb.res->buf->size : 0;
decode->dpb_size = (dec->dpb_type != DPB_DYNAMIC_TIER_2) ? dec->dpb.res->buf->base.size : 0;
/* When texture being created, the bo will be created with total size of planes,
* and all planes point to the same buffer */
assert(si_resource(((struct vl_video_buffer *)out_surf)->resources[0])->buf->size ==
si_resource(((struct vl_video_buffer *)out_surf)->resources[1])->buf->size);
assert(si_resource(((struct vl_video_buffer *)out_surf)->resources[0])->buf->base.size ==
si_resource(((struct vl_video_buffer *)out_surf)->resources[1])->buf->base.size);
decode->dt_size = si_resource(((struct vl_video_buffer *)out_surf)->resources[0])->buf->size;
decode->dt_size = si_resource(((struct vl_video_buffer *)out_surf)->resources[0])->buf->base.size;
decode->sct_size = 0;
decode->sc_coeff_size = 0;
@@ -2364,7 +2364,7 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
}
if (dec->ctx.res)
decode->hw_ctxt_size = dec->ctx.res->buf->size;
decode->hw_ctxt_size = dec->ctx.res->buf->base.size;
if (dec->dpb_type == DPB_DYNAMIC_TIER_2)
if (rvcn_dec_dynamic_dpb_t2_message(dec, decode, dynamic_dpb_t2, encrypted))
@@ -2882,7 +2882,7 @@ static void radeon_dec_decode_bitstream(struct pipe_video_codec *decoder,
struct rvid_buffer *buf = &dec->bs_buffers[dec->cur_buffer];
if (total_bs_size > buf->res->buf->size) {
if (total_bs_size > buf->res->buf->base.size) {
dec->ws->buffer_unmap(dec->ws, buf->res->buf);
dec->bs_ptr = NULL;
if (!si_vid_resize_buffer(dec->screen, &dec->cs, buf, total_bs_size, NULL)) {
src/gallium/drivers/radeonsi/radeon_vcn_enc.c
+1 -1
View File
@@ -1160,7 +1160,7 @@ static void radeon_enc_encode_bitstream(struct pipe_video_codec *encoder,
if (vid_buf->base.statistics_data) {
enc->get_buffer(vid_buf->base.statistics_data, &enc->stats, NULL);
if (enc->stats->size < sizeof(rvcn_encode_stats_type_0_t)) {
if (enc->stats->base.size < sizeof(rvcn_encode_stats_type_0_t)) {
RVID_ERR("Encoder statistics output buffer is too small.\n");
enc->stats = NULL;
}
src/gallium/drivers/radeonsi/radeon_video.c
+1 -1
View File
@@ -73,7 +73,7 @@ bool si_vid_resize_buffer(struct pipe_screen *screen, struct radeon_cmdbuf *cs,
{
struct si_screen *sscreen = (struct si_screen *)screen;
struct radeon_winsys *ws = sscreen->ws;
unsigned bytes = MIN2(new_buf->res->buf->size, new_size);
unsigned bytes = MIN2(new_buf->res->buf->base.size, new_size);
struct rvid_buffer old_buf = *new_buf;
void *src = NULL, *dst = NULL;
src/gallium/drivers/radeonsi/si_buffer.c
+4 -4
View File
@@ -179,7 +179,7 @@ bool si_alloc_resource(struct si_screen *sscreen, struct si_resource *res)
/* Print debug information. */
if (sscreen->debug_flags & DBG(VM) && res->b.b.target == PIPE_BUFFER) {
fprintf(stderr, "VM start=0x%" PRIX64 " end=0x%" PRIX64 " | Buffer %" PRIu64 " bytes | Flags: ",
res->gpu_address, res->gpu_address + res->buf->size, res->buf->size);
res->gpu_address, res->gpu_address + res->buf->base.size, res->buf->base.size);
si_res_print_flags(res->flags);
fprintf(stderr, "\n");
}
@@ -643,7 +643,7 @@ struct pipe_resource *si_buffer_from_winsys_buffer(struct pipe_screen *screen,
struct pb_buffer *imported_buf,
uint64_t offset)
{
if (offset + templ->width0 > imported_buf->size)
if (offset + templ->width0 > imported_buf->base.size)
return NULL;
struct si_screen *sscreen = (struct si_screen *)screen;
@@ -679,8 +679,8 @@ struct pipe_resource *si_buffer_from_winsys_buffer(struct pipe_screen *screen,
res->b.b.usage = PIPE_USAGE_STAGING;
}
si_init_resource_fields(sscreen, res, imported_buf->size,
1 << imported_buf->alignment_log2);
si_init_resource_fields(sscreen, res, imported_buf->base.size,
1 << imported_buf->base.alignment_log2);
res->b.is_shared = true;
res->b.buffer_id_unique = util_idalloc_mt_alloc(&sscreen->buffer_ids);
src/gallium/drivers/radeonsi/si_texture.c
+5 -5
View File
@@ -1007,8 +1007,8 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen,
} else {
resource->buf = imported_buf;
resource->gpu_address = sscreen->ws->buffer_get_virtual_address(resource->buf);
resource->bo_size = imported_buf->size;
resource->bo_alignment_log2 = imported_buf->alignment_log2;
resource->bo_size = imported_buf->base.size;
resource->bo_alignment_log2 = imported_buf->base.alignment_log2;
resource->domains = sscreen->ws->buffer_get_initial_domain(resource->buf);
if (sscreen->ws->buffer_get_flags)
resource->flags = sscreen->ws->buffer_get_flags(resource->buf);
@@ -1018,7 +1018,7 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen,
fprintf(stderr,
"VM start=0x%" PRIX64 " end=0x%" PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s | Flags: ",
tex->buffer.gpu_address, tex->buffer.gpu_address + tex->buffer.buf->size,
tex->buffer.gpu_address, tex->buffer.gpu_address + tex->buffer.buf->base.size,
base->width0, base->height0, util_num_layers(base, 0), base->last_level + 1,
base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
si_res_print_flags(tex->buffer.flags);
@@ -1681,7 +1681,7 @@ static struct pipe_resource *si_texture_from_winsys_buffer(struct si_screen *ssc
}
if (ac_surface_get_plane_offset(sscreen->info.gfx_level, &tex->surface, 0, 0) +
tex->surface.total_size > buf->size) {
tex->surface.total_size > buf->base.size) {
si_texture_reference(&tex, NULL);
return NULL;
}
@@ -2025,7 +2025,7 @@ static void si_texture_transfer_unmap(struct pipe_context *ctx, struct pipe_tran
si_copy_from_staging_texture(ctx, stransfer);
if (stransfer->staging) {
sctx->num_alloc_tex_transfer_bytes += stransfer->staging->buf->size;
sctx->num_alloc_tex_transfer_bytes += stransfer->staging->buf->base.size;
si_resource_reference(&stransfer->staging, NULL);
}
src/gallium/drivers/zink/zink_bo.c
+38 -38
View File
@@ -171,7 +171,7 @@ static void
bo_slab_free(struct zink_screen *screen, struct pb_slab *pslab)
{
struct zink_slab *slab = zink_slab(pslab);
ASSERTED unsigned slab_size = slab->buffer->base.size;
ASSERTED unsigned slab_size = slab->buffer->base.base.size;
assert(slab->base.num_entries * slab->base.entry_size <= slab_size);
FREE(slab->entries);
@@ -189,7 +189,7 @@ bo_slab_destroy(struct zink_screen *screen, struct pb_buffer *pbuf)
//if (bo->base.usage & RADEON_FLAG_ENCRYPTED)
//pb_slab_free(get_slabs(screen, bo->base.size, RADEON_FLAG_ENCRYPTED), &bo->u.slab.entry);
//else
pb_slab_free(get_slabs(screen, bo->base.size, 0), &bo->u.slab.entry);
pb_slab_free(get_slabs(screen, bo->base.base.size, 0), &bo->u.slab.entry);
}
static bool
@@ -320,12 +320,12 @@ bo_create_internal(struct zink_screen *screen,
simple_mtx_init(&bo->lock, mtx_plain);
pipe_reference_init(&bo->base.reference, 1);
bo->base.alignment_log2 = util_logbase2(alignment);
bo->base.size = mai.allocationSize;
pipe_reference_init(&bo->base.base.reference, 1);
bo->base.base.alignment_log2 = util_logbase2(alignment);
bo->base.base.size = mai.allocationSize;
bo->base.vtbl = &bo_vtbl;
bo->base.placement = mem_type_idx;
bo->base.usage = flags;
bo->base.base.placement = mem_type_idx;
bo->base.base.usage = flags;
bo->unique_id = p_atomic_inc_return(&screen->pb.next_bo_unique_id);
return bo;
@@ -383,11 +383,11 @@ sparse_backing_alloc(struct zink_screen *screen, struct zink_bo *bo,
return NULL;
}
assert(bo->u.sparse.num_backing_pages < DIV_ROUND_UP(bo->base.size, ZINK_SPARSE_BUFFER_PAGE_SIZE));
assert(bo->u.sparse.num_backing_pages < DIV_ROUND_UP(bo->base.base.size, ZINK_SPARSE_BUFFER_PAGE_SIZE));
size = MIN3(bo->base.size / 16,
size = MIN3(bo->base.base.size / 16,
8 * 1024 * 1024,
bo->base.size - (uint64_t)bo->u.sparse.num_backing_pages * ZINK_SPARSE_BUFFER_PAGE_SIZE);
bo->base.base.size - (uint64_t)bo->u.sparse.num_backing_pages * ZINK_SPARSE_BUFFER_PAGE_SIZE);
size = MAX2(size, ZINK_SPARSE_BUFFER_PAGE_SIZE);
buf = zink_bo_create(screen, size, ZINK_SPARSE_BUFFER_PAGE_SIZE,
@@ -399,7 +399,7 @@ sparse_backing_alloc(struct zink_screen *screen, struct zink_bo *bo,
}
/* We might have gotten a bigger buffer than requested via caching. */
pages = buf->size / ZINK_SPARSE_BUFFER_PAGE_SIZE;
pages = buf->base.size / ZINK_SPARSE_BUFFER_PAGE_SIZE;
best_backing->bo = zink_bo(buf);
best_backing->num_chunks = 1;
@@ -430,7 +430,7 @@ static void
sparse_free_backing_buffer(struct zink_screen *screen, struct zink_bo *bo,
struct zink_sparse_backing *backing)
{
bo->u.sparse.num_backing_pages -= backing->bo->base.size / ZINK_SPARSE_BUFFER_PAGE_SIZE;
bo->u.sparse.num_backing_pages -= backing->bo->base.base.size / ZINK_SPARSE_BUFFER_PAGE_SIZE;
list_del(&backing->list);
zink_bo_unref(screen, backing->bo);
@@ -497,7 +497,7 @@ sparse_backing_free(struct zink_screen *screen, struct zink_bo *bo,
}
if (backing->num_chunks == 1 && backing->chunks[0].begin == 0 &&
backing->chunks[0].end == backing->bo->base.size / ZINK_SPARSE_BUFFER_PAGE_SIZE)
backing->chunks[0].end == backing->bo->base.base.size / ZINK_SPARSE_BUFFER_PAGE_SIZE)
sparse_free_backing_buffer(screen, bo, backing);
return true;
@@ -508,7 +508,7 @@ bo_sparse_destroy(struct zink_screen *screen, struct pb_buffer *pbuf)
{
struct zink_bo *bo = zink_bo(pbuf);
assert(!bo->mem && bo->base.usage & ZINK_ALLOC_SPARSE);
assert(!bo->mem && bo->base.base.usage & ZINK_ALLOC_SPARSE);
while (!list_is_empty(&bo->u.sparse.backing)) {
sparse_free_backing_buffer(screen, bo,
@@ -544,15 +544,15 @@ bo_sparse_create(struct zink_screen *screen, uint64_t size)
return NULL;
simple_mtx_init(&bo->lock, mtx_plain);
pipe_reference_init(&bo->base.reference, 1);
bo->base.alignment_log2 = util_logbase2(ZINK_SPARSE_BUFFER_PAGE_SIZE);
bo->base.size = size;
pipe_reference_init(&bo->base.base.reference, 1);
bo->base.base.alignment_log2 = util_logbase2(ZINK_SPARSE_BUFFER_PAGE_SIZE);
bo->base.base.size = size;
bo->base.vtbl = &bo_sparse_vtbl;
unsigned placement = zink_mem_type_idx_from_bits(screen, ZINK_HEAP_DEVICE_LOCAL_SPARSE, VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT);
assert(placement != UINT32_MAX);
bo->base.placement = placement;
bo->base.base.placement = placement;
bo->unique_id = p_atomic_inc_return(&screen->pb.next_bo_unique_id);
bo->base.usage = ZINK_ALLOC_SPARSE;
bo->base.base.usage = ZINK_ALLOC_SPARSE;
bo->u.sparse.num_va_pages = DIV_ROUND_UP(size, ZINK_SPARSE_BUFFER_PAGE_SIZE);
bo->u.sparse.commitments = CALLOC(bo->u.sparse.num_va_pages,
@@ -633,10 +633,10 @@ zink_bo_create(struct zink_screen *screen, uint64_t size, unsigned alignment, en
return NULL;
bo = container_of(entry, struct zink_bo, u.slab.entry);
assert(bo->base.placement == mem_type_idx);
pipe_reference_init(&bo->base.reference, 1);
bo->base.size = size;
assert(alignment <= 1 << bo->base.alignment_log2);
assert(bo->base.base.placement == mem_type_idx);
pipe_reference_init(&bo->base.base.reference, 1);
bo->base.base.size = size;
assert(alignment <= 1 << bo->base.base.alignment_log2);
return &bo->base;
}
@@ -663,7 +663,7 @@ no_slab:
/* Get a buffer from the cache. */
bo = (struct zink_bo*)
pb_cache_reclaim_buffer(&screen->pb.bo_cache, size, alignment, 0, mem_type_idx);
assert(!bo || bo->base.placement == mem_type_idx);
assert(!bo || bo->base.base.placement == mem_type_idx);
if (bo)
return &bo->base;
}
@@ -677,7 +677,7 @@ no_slab:
if (!bo)
return NULL;
}
assert(bo->base.placement == mem_type_idx);
assert(bo->base.base.placement == mem_type_idx);
return &bo->base;
}
@@ -703,15 +703,15 @@ zink_bo_map(struct zink_screen *screen, struct zink_bo *bo)
* be atomic thanks to the lock. */
cpu = real->u.real.cpu_ptr;
if (!cpu) {
VkResult result = VKSCR(MapMemory)(screen->dev, real->mem, 0, real->base.size, 0, &cpu);
VkResult result = VKSCR(MapMemory)(screen->dev, real->mem, 0, real->base.base.size, 0, &cpu);
if (result != VK_SUCCESS) {
mesa_loge("ZINK: vkMapMemory failed (%s)", vk_Result_to_str(result));
simple_mtx_unlock(&real->lock);
return NULL;
}
if (unlikely(zink_debug & ZINK_DEBUG_MAP)) {
p_atomic_add(&screen->mapped_vram, real->base.size);
mesa_loge("NEW MAP(%"PRIu64") TOTAL(%"PRIu64")", real->base.size, screen->mapped_vram);
p_atomic_add(&screen->mapped_vram, real->base.base.size);
mesa_loge("NEW MAP(%"PRIu64") TOTAL(%"PRIu64")", real->base.base.size, screen->mapped_vram);
}
p_atomic_set(&real->u.real.cpu_ptr, cpu);
}
@@ -732,8 +732,8 @@ zink_bo_unmap(struct zink_screen *screen, struct zink_bo *bo)
if (p_atomic_dec_zero(&real->u.real.map_count)) {
p_atomic_set(&real->u.real.cpu_ptr, NULL);
if (unlikely(zink_debug & ZINK_DEBUG_MAP)) {
p_atomic_add(&screen->mapped_vram, -real->base.size);
mesa_loge("UNMAP(%"PRIu64") TOTAL(%"PRIu64")", real->base.size, screen->mapped_vram);
p_atomic_add(&screen->mapped_vram, -real->base.base.size);
mesa_loge("UNMAP(%"PRIu64") TOTAL(%"PRIu64")", real->base.base.size, screen->mapped_vram);
}
VKSCR(UnmapMemory)(screen->dev, real->mem);
}
@@ -743,7 +743,7 @@ zink_bo_unmap(struct zink_screen *screen, struct zink_bo *bo)
static void
track_freed_sparse_bo(struct zink_context *ctx, struct zink_sparse_backing *backing)
{
pipe_reference(NULL, &backing->bo->base.reference);
pipe_reference(NULL, &backing->bo->base.base.reference);
util_dynarray_append(&ctx->batch.state->freed_sparse_backing_bos, struct zink_bo*, backing->bo);
}
@@ -789,9 +789,9 @@ buffer_bo_commit(struct zink_context *ctx, struct zink_resource *res, uint32_t o
struct zink_screen *screen = zink_screen(ctx->base.screen);
struct zink_bo *bo = res->obj->bo;
assert(offset % ZINK_SPARSE_BUFFER_PAGE_SIZE == 0);
assert(offset <= bo->base.size);
assert(size <= bo->base.size - offset);
assert(size % ZINK_SPARSE_BUFFER_PAGE_SIZE == 0 || offset + size == bo->base.size);
assert(offset <= bo->base.base.size);
assert(size <= bo->base.base.size - offset);
assert(size % ZINK_SPARSE_BUFFER_PAGE_SIZE == 0 || offset + size == bo->base.base.size);
struct zink_sparse_commitment *comm = bo->u.sparse.commitments;
@@ -1237,7 +1237,7 @@ bo_slab_alloc(void *priv, unsigned mem_type_idx, unsigned entry_size, unsigned g
if (!slab->buffer)
goto fail;
slab_size = slab->buffer->base.size;
slab_size = slab->buffer->base.base.size;
slab->base.num_entries = slab_size / entry_size;
slab->base.num_free = slab->base.num_entries;
@@ -1254,8 +1254,8 @@ bo_slab_alloc(void *priv, unsigned mem_type_idx, unsigned entry_size, unsigned g
struct zink_bo *bo = &slab->entries[i];
simple_mtx_init(&bo->lock, mtx_plain);
bo->base.alignment_log2 = util_logbase2(get_slab_entry_alignment(screen, entry_size));
bo->base.size = entry_size;
bo->base.base.alignment_log2 = util_logbase2(get_slab_entry_alignment(screen, entry_size));
bo->base.base.size = entry_size;
bo->base.vtbl = &bo_slab_vtbl;
bo->offset = slab->buffer->offset + i * entry_size;
bo->unique_id = base_id + i;
@@ -1269,7 +1269,7 @@ bo_slab_alloc(void *priv, unsigned mem_type_idx, unsigned entry_size, unsigned g
bo->u.slab.real = slab->buffer->u.slab.real;
assert(bo->u.slab.real->mem);
}
bo->base.placement = bo->u.slab.real->base.placement;
bo->base.base.placement = bo->u.slab.real->base.base.placement;
list_addtail(&bo->u.slab.entry.head, &slab->base.free);
}
src/gallium/drivers/zink/zink_bo.h
+1 -1
View File
@@ -131,7 +131,7 @@ zink_bo_get_mem(const struct zink_bo *bo)
static ALWAYS_INLINE VkDeviceSize
zink_bo_get_size(const struct zink_bo *bo)
{
return bo->mem ? bo->base.size : bo->u.slab.real->base.size;
return bo->mem ? bo->base.base.size : bo->u.slab.real->base.base.size;
}
void *
src/gallium/drivers/zink/zink_resource.c
+3 -3
View File
@@ -1339,9 +1339,9 @@ retry:
obj->bo->name = zink_debug_mem_add(screen, obj->size, buf);
}
obj->coherent = screen->info.mem_props.memoryTypes[obj->bo->base.placement].propertyFlags & VK_MEMORY_PROPERTY_HOST_COHERENT_BIT;
obj->coherent = screen->info.mem_props.memoryTypes[obj->bo->base.base.placement].propertyFlags & VK_MEMORY_PROPERTY_HOST_COHERENT_BIT;
if (!(templ->flags & PIPE_RESOURCE_FLAG_SPARSE)) {
obj->host_visible = screen->info.mem_props.memoryTypes[obj->bo->base.placement].propertyFlags & VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT;
obj->host_visible = screen->info.mem_props.memoryTypes[obj->bo->base.base.placement].propertyFlags & VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT;
}
if (templ->target == PIPE_BUFFER) {
@@ -2203,7 +2203,7 @@ zink_buffer_map(struct pipe_context *pctx,
usage |= PIPE_MAP_UNSYNCHRONIZED;
} else if (!(usage & PIPE_MAP_UNSYNCHRONIZED) &&
(((usage & PIPE_MAP_READ) && !(usage & PIPE_MAP_PERSISTENT) &&
((screen->info.mem_props.memoryTypes[res->obj->bo->base.placement].propertyFlags & VK_STAGING_RAM) != VK_STAGING_RAM)) ||
((screen->info.mem_props.memoryTypes[res->obj->bo->base.base.placement].propertyFlags & VK_STAGING_RAM) != VK_STAGING_RAM)) ||
!res->obj->host_visible)) {
/* the above conditional catches uncached reads and non-HV writes */
assert(!(usage & (TC_TRANSFER_MAP_THREADED_UNSYNC)));
src/gallium/include/winsys/radeon_winsys.h
+1 -1
View File
@@ -785,7 +785,7 @@ radeon_bo_reference(struct radeon_winsys *rws, struct pb_buffer **dst, struct pb
{
struct pb_buffer *old = *dst;
if (pipe_reference(&(*dst)->reference, &src->reference))
if (pipe_reference(&(*dst)->base.reference, &src->base.reference))
rws->buffer_destroy(rws, old);
*dst = src;
}
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+68 -68
View File
@@ -137,13 +137,13 @@ static inline unsigned get_slab_entry_offset(struct amdgpu_winsys_bo *bo)
static enum radeon_bo_domain amdgpu_bo_get_initial_domain(
struct pb_buffer *buf)
{
return ((struct amdgpu_winsys_bo*)buf)->base.placement;
return ((struct amdgpu_winsys_bo*)buf)->base.base.placement;
}
static enum radeon_bo_flag amdgpu_bo_get_flags(
struct pb_buffer *buf)
{
return ((struct amdgpu_winsys_bo*)buf)->base.usage;
return ((struct amdgpu_winsys_bo*)buf)->base.base.usage;
}
static void amdgpu_bo_remove_fences(struct amdgpu_winsys_bo *bo)
@@ -164,15 +164,15 @@ void amdgpu_bo_destroy(struct amdgpu_winsys *ws, struct pb_buffer *_buf)
simple_mtx_lock(&ws->bo_export_table_lock);
/* amdgpu_bo_from_handle might have revived the bo */
if (p_atomic_read(&bo->b.base.reference.count)) {
if (p_atomic_read(&bo->b.base.base.reference.count)) {
simple_mtx_unlock(&ws->bo_export_table_lock);
return;
}
_mesa_hash_table_remove_key(ws->bo_export_table, bo->bo);
if (bo->b.base.placement & RADEON_DOMAIN_VRAM_GTT) {
amdgpu_bo_va_op(bo->bo, 0, bo->b.base.size, bo->gpu_address, 0, AMDGPU_VA_OP_UNMAP);
if (bo->b.base.base.placement & RADEON_DOMAIN_VRAM_GTT) {
amdgpu_bo_va_op(bo->bo, 0, bo->b.base.base.size, bo->gpu_address, 0, AMDGPU_VA_OP_UNMAP);
amdgpu_va_range_free(bo->va_handle);
}
@@ -215,10 +215,10 @@ void amdgpu_bo_destroy(struct amdgpu_winsys *ws, struct pb_buffer *_buf)
amdgpu_bo_remove_fences(&bo->b);
if (bo->b.base.placement & RADEON_DOMAIN_VRAM)
ws->allocated_vram -= align64(bo->b.base.size, ws->info.gart_page_size);
else if (bo->b.base.placement & RADEON_DOMAIN_GTT)
ws->allocated_gtt -= align64(bo->b.base.size, ws->info.gart_page_size);
if (bo->b.base.base.placement & RADEON_DOMAIN_VRAM)
ws->allocated_vram -= align64(bo->b.base.base.size, ws->info.gart_page_size);
else if (bo->b.base.base.placement & RADEON_DOMAIN_GTT)
ws->allocated_gtt -= align64(bo->b.base.base.size, ws->info.gart_page_size);
simple_mtx_destroy(&bo->lock);
FREE(bo);
@@ -259,10 +259,10 @@ static bool amdgpu_bo_do_map(struct radeon_winsys *rws, struct amdgpu_bo_real *b
}
if (p_atomic_inc_return(&bo->map_count) == 1) {
if (bo->b.base.placement & RADEON_DOMAIN_VRAM)
ws->mapped_vram += bo->b.base.size;
else if (bo->b.base.placement & RADEON_DOMAIN_GTT)
ws->mapped_gtt += bo->b.base.size;
if (bo->b.base.base.placement & RADEON_DOMAIN_VRAM)
ws->mapped_vram += bo->b.base.base.size;
else if (bo->b.base.base.placement & RADEON_DOMAIN_GTT)
ws->mapped_gtt += bo->b.base.base.size;
ws->num_mapped_buffers++;
}
@@ -419,10 +419,10 @@ void amdgpu_bo_unmap(struct radeon_winsys *rws, struct pb_buffer *buf)
assert(!real->cpu_ptr &&
"too many unmaps or forgot RADEON_MAP_TEMPORARY flag");
if (real->b.base.placement & RADEON_DOMAIN_VRAM)
ws->mapped_vram -= real->b.base.size;
else if (real->b.base.placement & RADEON_DOMAIN_GTT)
ws->mapped_gtt -= real->b.base.size;
if (real->b.base.base.placement & RADEON_DOMAIN_VRAM)
ws->mapped_vram -= real->b.base.base.size;
else if (real->b.base.base.placement & RADEON_DOMAIN_GTT)
ws->mapped_gtt -= real->b.base.base.size;
ws->num_mapped_buffers--;
}
@@ -587,11 +587,11 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *ws,
}
simple_mtx_init(&bo->lock, mtx_plain);
pipe_reference_init(&bo->b.base.reference, 1);
bo->b.base.placement = initial_domain;
bo->b.base.alignment_log2 = util_logbase2(alignment);
bo->b.base.usage = flags;
bo->b.base.size = size;
pipe_reference_init(&bo->b.base.base.reference, 1);
bo->b.base.base.placement = initial_domain;
bo->b.base.base.alignment_log2 = util_logbase2(alignment);
bo->b.base.base.usage = flags;
bo->b.base.base.size = size;
bo->gpu_address = va;
bo->b.unique_id = __sync_fetch_and_add(&ws->next_bo_unique_id, 1);
bo->bo = buf_handle;
@@ -632,11 +632,11 @@ bool amdgpu_bo_can_reclaim_slab(void *priv, struct pb_slab_entry *entry)
static unsigned get_slab_wasted_size(struct amdgpu_winsys *ws, struct amdgpu_bo_slab_entry *bo)
{
assert(bo->b.base.size <= bo->entry.slab->entry_size);
assert(bo->b.base.size < (1 << bo->b.base.alignment_log2) ||
bo->b.base.size < 1 << ws->bo_slabs.min_order ||
bo->b.base.size > bo->entry.slab->entry_size / 2);
return bo->entry.slab->entry_size - bo->b.base.size;
assert(bo->b.base.base.size <= bo->entry.slab->entry_size);
assert(bo->b.base.base.size < (1 << bo->b.base.base.alignment_log2) ||
bo->b.base.base.size < 1 << ws->bo_slabs.min_order ||
bo->b.base.base.size > bo->entry.slab->entry_size / 2);
return bo->entry.slab->entry_size - bo->b.base.base.size;
}
static void amdgpu_bo_slab_destroy(struct radeon_winsys *rws, struct pb_buffer *_buf)
@@ -644,7 +644,7 @@ static void amdgpu_bo_slab_destroy(struct radeon_winsys *rws, struct pb_buffer *
struct amdgpu_winsys *ws = amdgpu_winsys(rws);
struct amdgpu_bo_slab_entry *bo = get_slab_entry_bo(amdgpu_winsys_bo(_buf));
if (bo->b.base.placement & RADEON_DOMAIN_VRAM)
if (bo->b.base.base.placement & RADEON_DOMAIN_VRAM)
ws->slab_wasted_vram -= get_slab_wasted_size(ws, bo);
else
ws->slab_wasted_gtt -= get_slab_wasted_size(ws, bo);
@@ -723,7 +723,7 @@ struct pb_slab *amdgpu_bo_slab_alloc(void *priv, unsigned heap, unsigned entry_s
assert(slab_bo->b.b.b.type == AMDGPU_BO_REAL_REUSABLE_SLAB);
/* We can get a buffer from pb_cache that is slightly larger. */
slab_size = slab_bo->b.b.b.base.size;
slab_size = slab_bo->b.b.b.base.base.size;
slab_bo->slab.num_entries = slab_size / entry_size;
slab_bo->slab.num_free = slab_bo->slab.num_entries;
@@ -740,9 +740,9 @@ struct pb_slab *amdgpu_bo_slab_alloc(void *priv, unsigned heap, unsigned entry_s
for (unsigned i = 0; i < slab_bo->slab.num_entries; ++i) {
struct amdgpu_bo_slab_entry *bo = &slab_bo->entries[i];
bo->b.base.placement = domains;
bo->b.base.alignment_log2 = util_logbase2(get_slab_entry_alignment(ws, entry_size));
bo->b.base.size = entry_size;
bo->b.base.base.placement = domains;
bo->b.base.base.alignment_log2 = util_logbase2(get_slab_entry_alignment(ws, entry_size));
bo->b.base.base.size = entry_size;
bo->b.type = AMDGPU_BO_SLAB_ENTRY;
bo->b.unique_id = base_id + i;
@@ -767,10 +767,10 @@ fail:
void amdgpu_bo_slab_free(struct amdgpu_winsys *ws, struct pb_slab *slab)
{
struct amdgpu_bo_real_reusable_slab *bo = get_bo_from_slab(slab);
unsigned slab_size = bo->b.b.b.base.size;
unsigned slab_size = bo->b.b.b.base.base.size;
assert(bo->slab.num_entries * bo->slab.entry_size <= slab_size);
if (bo->b.b.b.base.placement & RADEON_DOMAIN_VRAM)
if (bo->b.b.b.base.base.placement & RADEON_DOMAIN_VRAM)
ws->slab_wasted_vram -= slab_size - bo->slab.num_entries * bo->slab.entry_size;
else
ws->slab_wasted_gtt -= slab_size - bo->slab.num_entries * bo->slab.entry_size;
@@ -885,16 +885,16 @@ sparse_backing_alloc(struct amdgpu_winsys *ws, struct amdgpu_bo_sparse *bo,
return NULL;
}
assert(bo->num_backing_pages < DIV_ROUND_UP(bo->b.base.size, RADEON_SPARSE_PAGE_SIZE));
assert(bo->num_backing_pages < DIV_ROUND_UP(bo->b.base.base.size, RADEON_SPARSE_PAGE_SIZE));
size = MIN3(bo->b.base.size / 16,
size = MIN3(bo->b.base.base.size / 16,
8 * 1024 * 1024,
bo->b.base.size - (uint64_t)bo->num_backing_pages * RADEON_SPARSE_PAGE_SIZE);
bo->b.base.base.size - (uint64_t)bo->num_backing_pages * RADEON_SPARSE_PAGE_SIZE);
size = MAX2(size, RADEON_SPARSE_PAGE_SIZE);
buf = amdgpu_bo_create(ws, size, RADEON_SPARSE_PAGE_SIZE,
bo->b.base.placement,
(bo->b.base.usage & ~RADEON_FLAG_SPARSE &
bo->b.base.base.placement,
(bo->b.base.base.usage & ~RADEON_FLAG_SPARSE &
/* Set the interprocess sharing flag to disable pb_cache because
* amdgpu_bo_wait doesn't wait for active CS jobs.
*/
@@ -906,7 +906,7 @@ sparse_backing_alloc(struct amdgpu_winsys *ws, struct amdgpu_bo_sparse *bo,
}
/* We might have gotten a bigger buffer than requested via caching. */
pages = buf->size / RADEON_SPARSE_PAGE_SIZE;
pages = buf->base.size / RADEON_SPARSE_PAGE_SIZE;
best_backing->bo = get_real_bo(amdgpu_winsys_bo(buf));
best_backing->num_chunks = 1;
@@ -937,7 +937,7 @@ static void
sparse_free_backing_buffer(struct amdgpu_winsys *ws, struct amdgpu_bo_sparse *bo,
struct amdgpu_sparse_backing *backing)
{
bo->num_backing_pages -= backing->bo->b.base.size / RADEON_SPARSE_PAGE_SIZE;
bo->num_backing_pages -= backing->bo->b.base.base.size / RADEON_SPARSE_PAGE_SIZE;
simple_mtx_lock(&ws->bo_fence_lock);
amdgpu_add_fences(&backing->bo->b, bo->b.num_fences, bo->b.fences);
@@ -1008,7 +1008,7 @@ sparse_backing_free(struct amdgpu_winsys *ws, struct amdgpu_bo_sparse *bo,
}
if (backing->num_chunks == 1 && backing->chunks[0].begin == 0 &&
backing->chunks[0].end == backing->bo->b.base.size / RADEON_SPARSE_PAGE_SIZE)
backing->chunks[0].end == backing->bo->b.base.base.size / RADEON_SPARSE_PAGE_SIZE)
sparse_free_backing_buffer(ws, bo, backing);
return true;
@@ -1061,11 +1061,11 @@ amdgpu_bo_sparse_create(struct amdgpu_winsys *ws, uint64_t size,
return NULL;
simple_mtx_init(&bo->lock, mtx_plain);
pipe_reference_init(&bo->b.base.reference, 1);
bo->b.base.placement = domain;
bo->b.base.alignment_log2 = util_logbase2(RADEON_SPARSE_PAGE_SIZE);
bo->b.base.usage = flags;
bo->b.base.size = size;
pipe_reference_init(&bo->b.base.base.reference, 1);
bo->b.base.base.placement = domain;
bo->b.base.base.alignment_log2 = util_logbase2(RADEON_SPARSE_PAGE_SIZE);
bo->b.base.base.usage = flags;
bo->b.base.base.size = size;
bo->b.unique_id = __sync_fetch_and_add(&ws->next_bo_unique_id, 1);
bo->b.type = AMDGPU_BO_SPARSE;
@@ -1115,9 +1115,9 @@ amdgpu_bo_sparse_commit(struct radeon_winsys *rws, struct pb_buffer *buf,
int r;
assert(offset % RADEON_SPARSE_PAGE_SIZE == 0);
assert(offset <= bo->b.base.size);
assert(size <= bo->b.base.size - offset);
assert(size % RADEON_SPARSE_PAGE_SIZE == 0 || offset + size == bo->b.base.size);
assert(offset <= bo->b.base.base.size);
assert(size <= bo->b.base.base.size - offset);
assert(size % RADEON_SPARSE_PAGE_SIZE == 0 || offset + size == bo->b.base.base.size);
comm = bo->commitments;
va_page = offset / RADEON_SPARSE_PAGE_SIZE;
@@ -1245,7 +1245,7 @@ amdgpu_bo_find_next_committed_memory(struct pb_buffer *buf,
if (*range_size == 0)
return 0;
assert(*range_size + range_offset <= bo->b.base.size);
assert(*range_size + range_offset <= bo->b.base.base.size);
uncommitted_range_prev = uncommitted_range_next = 0;
comm = bo->commitments;
@@ -1381,9 +1381,9 @@ amdgpu_bo_create(struct amdgpu_winsys *ws,
return NULL;
struct amdgpu_bo_slab_entry *slab_bo = container_of(entry, struct amdgpu_bo_slab_entry, entry);
pipe_reference_init(&slab_bo->b.base.reference, 1);
slab_bo->b.base.size = size;
assert(alignment <= 1 << slab_bo->b.base.alignment_log2);
pipe_reference_init(&slab_bo->b.base.base.reference, 1);
slab_bo->b.base.base.size = size;
assert(alignment <= 1 << slab_bo->b.base.base.alignment_log2);
if (domain & RADEON_DOMAIN_VRAM)
ws->slab_wasted_vram += get_slab_wasted_size(ws, slab_bo);
@@ -1505,7 +1505,7 @@ static struct pb_buffer *amdgpu_bo_from_handle(struct radeon_winsys *rws,
* counter and return it.
*/
if (bo) {
p_atomic_inc(&bo->b.base.reference.count);
p_atomic_inc(&bo->b.base.base.reference.count);
simple_mtx_unlock(&ws->bo_export_table_lock);
/* Release the buffer handle, because we don't need it anymore.
@@ -1559,12 +1559,12 @@ static struct pb_buffer *amdgpu_bo_from_handle(struct radeon_winsys *rws,
}
/* Initialize the structure. */
pipe_reference_init(&bo->b.base.reference, 1);
bo->b.base.placement = initial;
bo->b.base.alignment_log2 = util_logbase2(info.phys_alignment ?
pipe_reference_init(&bo->b.base.base.reference, 1);
bo->b.base.base.placement = initial;
bo->b.base.base.alignment_log2 = util_logbase2(info.phys_alignment ?
info.phys_alignment : ws->info.gart_page_size);
bo->b.base.usage = flags;
bo->b.base.size = result.alloc_size;
bo->b.base.base.usage = flags;
bo->b.base.base.size = result.alloc_size;
bo->b.type = AMDGPU_BO_REAL;
bo->gpu_address = va;
bo->b.unique_id = __sync_fetch_and_add(&ws->next_bo_unique_id, 1);
@@ -1573,10 +1573,10 @@ static struct pb_buffer *amdgpu_bo_from_handle(struct radeon_winsys *rws,
bo->va_handle = va_handle;
bo->is_shared = true;
if (bo->b.base.placement & RADEON_DOMAIN_VRAM)
ws->allocated_vram += align64(bo->b.base.size, ws->info.gart_page_size);
else if (bo->b.base.placement & RADEON_DOMAIN_GTT)
ws->allocated_gtt += align64(bo->b.base.size, ws->info.gart_page_size);
if (bo->b.base.base.placement & RADEON_DOMAIN_VRAM)
ws->allocated_vram += align64(bo->b.base.base.size, ws->info.gart_page_size);
else if (bo->b.base.base.placement & RADEON_DOMAIN_GTT)
ws->allocated_gtt += align64(bo->b.base.base.size, ws->info.gart_page_size);
amdgpu_bo_export(bo->bo, amdgpu_bo_handle_type_kms, &bo->kms_handle);
@@ -1715,10 +1715,10 @@ static struct pb_buffer *amdgpu_bo_from_ptr(struct radeon_winsys *rws,
/* Initialize it. */
bo->is_user_ptr = true;
pipe_reference_init(&bo->b.base.reference, 1);
bo->b.base.placement = RADEON_DOMAIN_GTT;
bo->b.base.alignment_log2 = 0;
bo->b.base.size = size;
pipe_reference_init(&bo->b.base.base.reference, 1);
bo->b.base.base.placement = RADEON_DOMAIN_GTT;
bo->b.base.base.alignment_log2 = 0;
bo->b.base.base.size = size;
bo->b.type = AMDGPU_BO_REAL;
bo->gpu_address = va;
bo->b.unique_id = __sync_fetch_and_add(&ws->next_bo_unique_id, 1);
src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
+1 -1
View File
@@ -153,7 +153,7 @@ static struct amdgpu_bo_real_reusable *get_real_bo_reusable(struct amdgpu_winsys
static struct amdgpu_bo_sparse *get_sparse_bo(struct amdgpu_winsys_bo *bo)
{
assert(bo->type == AMDGPU_BO_SPARSE && bo->base.usage & RADEON_FLAG_SPARSE);
assert(bo->type == AMDGPU_BO_SPARSE && bo->base.base.usage & RADEON_FLAG_SPARSE);
return (struct amdgpu_bo_sparse*)bo;
}
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+4 -4
View File
@@ -795,7 +795,7 @@ static bool amdgpu_get_new_ib(struct amdgpu_winsys *ws,
/* Allocate a new buffer for IBs if the current buffer is all used. */
if (!main_ib->big_buffer ||
main_ib->used_ib_space + ib_size > main_ib->big_buffer->size) {
main_ib->used_ib_space + ib_size > main_ib->big_buffer->base.size) {
if (!amdgpu_ib_new_buffer(ws, main_ib, cs))
return false;
}
@@ -814,7 +814,7 @@ static bool amdgpu_get_new_ib(struct amdgpu_winsys *ws,
cs->csc->ib_main_addr = rcs->current.buf;
ib_size = main_ib->big_buffer->size - main_ib->used_ib_space;
ib_size = main_ib->big_buffer->base.size - main_ib->used_ib_space;
rcs->current.max_dw = ib_size / 4 - amdgpu_cs_epilog_dws(cs);
return true;
}
@@ -1146,7 +1146,7 @@ static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw)
rcs->current.cdw = 0;
rcs->current.buf = (uint32_t*)(main_ib->big_buffer_cpu_ptr + main_ib->used_ib_space);
rcs->current.max_dw = main_ib->big_buffer->size / 4 - cs_epilog_dw;
rcs->current.max_dw = main_ib->big_buffer->base.size / 4 - cs_epilog_dw;
amdgpu_cs_add_buffer(rcs, main_ib->big_buffer,
RADEON_USAGE_READ | RADEON_PRIO_IB, 0);
@@ -1163,7 +1163,7 @@ static unsigned amdgpu_cs_get_buffer_list(struct radeon_cmdbuf *rcs,
if (list) {
for (unsigned i = 0; i < num_real_buffers; i++) {
list[i].bo_size = real_buffers->buffers[i].bo->base.size;
list[i].bo_size = real_buffers->buffers[i].bo->base.base.size;
list[i].vm_address = get_real_bo(real_buffers->buffers[i].bo)->gpu_address;
list[i].priority_usage = real_buffers->buffers[i].usage;
}
src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+35 -35
View File
@@ -339,7 +339,7 @@ void radeon_bo_destroy(void *winsys, struct pb_buffer *_buf)
mtx_lock(&rws->bo_handles_mutex);
/* radeon_winsys_bo_from_handle might have revived the bo */
if (pipe_is_referenced(&bo->base.reference)) {
if (pipe_is_referenced(&bo->base.base.reference)) {
mtx_unlock(&rws->bo_handles_mutex);
return;
}
@@ -351,7 +351,7 @@ void radeon_bo_destroy(void *winsys, struct pb_buffer *_buf)
mtx_unlock(&rws->bo_handles_mutex);
if (bo->u.real.ptr)
os_munmap(bo->u.real.ptr, bo->base.size);
os_munmap(bo->u.real.ptr, bo->base.base.size);
if (rws->info.r600_has_virtual_memory) {
if (rws->va_unmap_working) {
@@ -369,14 +369,14 @@ void radeon_bo_destroy(void *winsys, struct pb_buffer *_buf)
sizeof(va)) != 0 &&
va.operation == RADEON_VA_RESULT_ERROR) {
fprintf(stderr, "radeon: Failed to deallocate virtual address for buffer:\n");
fprintf(stderr, "radeon: size : %"PRIu64" bytes\n", bo->base.size);
fprintf(stderr, "radeon: size : %"PRIu64" bytes\n", bo->base.base.size);
fprintf(stderr, "radeon: va : 0x%"PRIx64"\n", bo->va);
}
}
radeon_bomgr_free_va(&rws->info,
bo->va < rws->vm32.end ? &rws->vm32 : &rws->vm64,
bo->va, bo->base.size);
bo->va, bo->base.base.size);
}
/* Close object. */
@@ -386,15 +386,15 @@ void radeon_bo_destroy(void *winsys, struct pb_buffer *_buf)
mtx_destroy(&bo->u.real.map_mutex);
if (bo->initial_domain & RADEON_DOMAIN_VRAM)
rws->allocated_vram -= align(bo->base.size, rws->info.gart_page_size);
rws->allocated_vram -= align(bo->base.base.size, rws->info.gart_page_size);
else if (bo->initial_domain & RADEON_DOMAIN_GTT)
rws->allocated_gtt -= align(bo->base.size, rws->info.gart_page_size);
rws->allocated_gtt -= align(bo->base.base.size, rws->info.gart_page_size);
if (bo->u.real.map_count >= 1) {
if (bo->initial_domain & RADEON_DOMAIN_VRAM)
bo->rws->mapped_vram -= bo->base.size;
bo->rws->mapped_vram -= bo->base.base.size;
else
bo->rws->mapped_gtt -= bo->base.size;
bo->rws->mapped_gtt -= bo->base.base.size;
bo->rws->num_mapped_buffers--;
}
@@ -440,7 +440,7 @@ void *radeon_bo_do_map(struct radeon_bo *bo)
}
args.handle = bo->handle;
args.offset = 0;
args.size = (uint64_t)bo->base.size;
args.size = (uint64_t)bo->base.base.size;
if (drmCommandWriteRead(bo->rws->fd,
DRM_RADEON_GEM_MMAP,
&args,
@@ -469,9 +469,9 @@ void *radeon_bo_do_map(struct radeon_bo *bo)
bo->u.real.map_count = 1;
if (bo->initial_domain & RADEON_DOMAIN_VRAM)
bo->rws->mapped_vram += bo->base.size;
bo->rws->mapped_vram += bo->base.base.size;
else
bo->rws->mapped_gtt += bo->base.size;
bo->rws->mapped_gtt += bo->base.base.size;
bo->rws->num_mapped_buffers++;
mtx_unlock(&bo->u.real.map_mutex);
@@ -583,13 +583,13 @@ static void radeon_bo_unmap(struct radeon_winsys *rws, struct pb_buffer *_buf)
return; /* it's been mapped multiple times */
}
os_munmap(bo->u.real.ptr, bo->base.size);
os_munmap(bo->u.real.ptr, bo->base.base.size);
bo->u.real.ptr = NULL;
if (bo->initial_domain & RADEON_DOMAIN_VRAM)
bo->rws->mapped_vram -= bo->base.size;
bo->rws->mapped_vram -= bo->base.base.size;
else
bo->rws->mapped_gtt -= bo->base.size;
bo->rws->mapped_gtt -= bo->base.base.size;
bo->rws->num_mapped_buffers--;
mtx_unlock(&bo->u.real.map_mutex);
@@ -649,10 +649,10 @@ static struct radeon_bo *radeon_create_bo(struct radeon_drm_winsys *rws,
if (!bo)
return NULL;
pipe_reference_init(&bo->base.reference, 1);
bo->base.alignment_log2 = util_logbase2(alignment);
bo->base.usage = 0;
bo->base.size = size;
pipe_reference_init(&bo->base.base.reference, 1);
bo->base.base.alignment_log2 = util_logbase2(alignment);
bo->base.base.usage = 0;
bo->base.base.size = size;
bo->base.vtbl = &radeon_bo_vtbl;
bo->rws = rws;
bo->handle = args.handle;
@@ -772,7 +772,7 @@ struct pb_slab *radeon_bo_slab_alloc(void *priv, unsigned heap,
assert(slab->buffer->handle);
slab->base.num_entries = slab->buffer->base.size / entry_size;
slab->base.num_entries = slab->buffer->base.base.size / entry_size;
slab->base.num_free = slab->base.num_entries;
slab->base.group_index = group_index;
slab->base.entry_size = entry_size;
@@ -787,9 +787,9 @@ struct pb_slab *radeon_bo_slab_alloc(void *priv, unsigned heap,
for (unsigned i = 0; i < slab->base.num_entries; ++i) {
struct radeon_bo *bo = &slab->entries[i];
bo->base.alignment_log2 = util_logbase2(entry_size);
bo->base.usage = slab->buffer->base.usage;
bo->base.size = entry_size;
bo->base.base.alignment_log2 = util_logbase2(entry_size);
bo->base.base.usage = slab->buffer->base.base.usage;
bo->base.base.size = entry_size;
bo->base.vtbl = &radeon_winsys_bo_slab_vtbl;
bo->rws = ws;
bo->va = slab->buffer->va + i * entry_size;
@@ -1024,7 +1024,7 @@ radeon_winsys_bo_create(struct radeon_winsys *rws,
bo = container_of(entry, struct radeon_bo, u.slab.entry);
pipe_reference_init(&bo->base.reference, 1);
pipe_reference_init(&bo->base.base.reference, 1);
return &bo->base;
}
@@ -1112,10 +1112,10 @@ static struct pb_buffer *radeon_winsys_bo_from_ptr(struct radeon_winsys *rws,
mtx_lock(&ws->bo_handles_mutex);
/* Initialize it. */
pipe_reference_init(&bo->base.reference, 1);
pipe_reference_init(&bo->base.base.reference, 1);
bo->handle = args.handle;
bo->base.alignment_log2 = 0;
bo->base.size = size;
bo->base.base.alignment_log2 = 0;
bo->base.base.size = size;
bo->base.vtbl = &radeon_bo_vtbl;
bo->rws = ws;
bo->user_ptr = pointer;
@@ -1131,7 +1131,7 @@ static struct pb_buffer *radeon_winsys_bo_from_ptr(struct radeon_winsys *rws,
if (ws->info.r600_has_virtual_memory) {
struct drm_radeon_gem_va va;
bo->va = radeon_bomgr_find_va64(ws, bo->base.size, 1 << 20);
bo->va = radeon_bomgr_find_va64(ws, bo->base.base.size, 1 << 20);
va.handle = bo->handle;
va.operation = RADEON_VA_MAP;
@@ -1162,7 +1162,7 @@ static struct pb_buffer *radeon_winsys_bo_from_ptr(struct radeon_winsys *rws,
mtx_unlock(&ws->bo_handles_mutex);
}
ws->allocated_gtt += align(bo->base.size, ws->info.gart_page_size);
ws->allocated_gtt += align(bo->base.base.size, ws->info.gart_page_size);
return (struct pb_buffer*)bo;
}
@@ -1202,7 +1202,7 @@ static struct pb_buffer *radeon_winsys_bo_from_handle(struct radeon_winsys *rws,
if (bo) {
/* Increase the refcount. */
p_atomic_inc(&bo->base.reference.count);
p_atomic_inc(&bo->base.base.reference.count);
goto done;
}
@@ -1242,9 +1242,9 @@ static struct pb_buffer *radeon_winsys_bo_from_handle(struct radeon_winsys *rws,
bo->handle = handle;
/* Initialize it. */
pipe_reference_init(&bo->base.reference, 1);
bo->base.alignment_log2 = 0;
bo->base.size = (unsigned) size;
pipe_reference_init(&bo->base.base.reference, 1);
bo->base.base.alignment_log2 = 0;
bo->base.base.size = (unsigned) size;
bo->base.vtbl = &radeon_bo_vtbl;
bo->rws = ws;
bo->va = 0;
@@ -1262,7 +1262,7 @@ done:
if (ws->info.r600_has_virtual_memory && !bo->va) {
struct drm_radeon_gem_va va;
bo->va = radeon_bomgr_find_va64(ws, bo->base.size, vm_alignment);
bo->va = radeon_bomgr_find_va64(ws, bo->base.base.size, vm_alignment);
va.handle = bo->handle;
va.operation = RADEON_VA_MAP;
@@ -1296,9 +1296,9 @@ done:
bo->initial_domain = radeon_bo_get_initial_domain((void*)bo);
if (bo->initial_domain & RADEON_DOMAIN_VRAM)
ws->allocated_vram += align(bo->base.size, ws->info.gart_page_size);
ws->allocated_vram += align(bo->base.base.size, ws->info.gart_page_size);
else if (bo->initial_domain & RADEON_DOMAIN_GTT)
ws->allocated_gtt += align(bo->base.size, ws->info.gart_page_size);
ws->allocated_gtt += align(bo->base.base.size, ws->info.gart_page_size);
return (struct pb_buffer*)bo;
src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+3 -3
View File
@@ -415,9 +415,9 @@ static unsigned radeon_drm_cs_add_buffer(struct radeon_cmdbuf *rcs,
cs->csc->relocs_bo[index].u.real.priority_usage |= priority;
if (added_domains & RADEON_DOMAIN_VRAM)
rcs->used_vram_kb += bo->base.size / 1024;
rcs->used_vram_kb += bo->base.base.size / 1024;
else if (added_domains & RADEON_DOMAIN_GTT)
rcs->used_gart_kb += bo->base.size / 1024;
rcs->used_gart_kb += bo->base.base.size / 1024;
return index;
}
@@ -483,7 +483,7 @@ static unsigned radeon_drm_cs_get_buffer_list(struct radeon_cmdbuf *rcs,
if (list) {
for (i = 0; i < cs->csc->num_relocs; i++) {
list[i].bo_size = cs->csc->relocs_bo[i].bo->base.size;
list[i].bo_size = cs->csc->relocs_bo[i].bo->base.base.size;
list[i].vm_address = cs->csc->relocs_bo[i].bo->va;
list[i].priority_usage = cs->csc->relocs_bo[i].u.real.priority_usage;
}
src/gallium/winsys/svga/drm/pb_buffer_simple_fenced.c
+16 -16
View File
@@ -175,8 +175,8 @@ fenced_manager_dump_locked(struct fenced_manager *fenced_mgr)
assert(!fenced_buf->fence);
debug_printf("%10p %"PRIu64" %8u %7s\n",
(void *) fenced_buf,
fenced_buf->base.size,
p_atomic_read(&fenced_buf->base.reference.count),
fenced_buf->base.base.size,
p_atomic_read(&fenced_buf->base.base.reference.count),
fenced_buf->buffer ? "gpu" : "none");
curr = next;
next = curr->next;
@@ -191,8 +191,8 @@ fenced_manager_dump_locked(struct fenced_manager *fenced_mgr)
signaled = ops->fence_signalled(ops, fenced_buf->fence, 0);
debug_printf("%10p %"PRIu64" %8u %7s %10p %s\n",
(void *) fenced_buf,
fenced_buf->base.size,
p_atomic_read(&fenced_buf->base.reference.count),
fenced_buf->base.base.size,
p_atomic_read(&fenced_buf->base.base.reference.count),
"gpu",
(void *) fenced_buf->fence,
signaled == 0 ? "y" : "n");
@@ -209,7 +209,7 @@ static inline void
fenced_buffer_destroy_locked(struct fenced_manager *fenced_mgr,
struct fenced_buffer *fenced_buf)
{
assert(!pipe_is_referenced(&fenced_buf->base.reference));
assert(!pipe_is_referenced(&fenced_buf->base.base.reference));
assert(!fenced_buf->fence);
assert(fenced_buf->head.prev);
@@ -233,11 +233,11 @@ static inline void
fenced_buffer_add_locked(struct fenced_manager *fenced_mgr,
struct fenced_buffer *fenced_buf)
{
assert(pipe_is_referenced(&fenced_buf->base.reference));
assert(pipe_is_referenced(&fenced_buf->base.base.reference));
assert(fenced_buf->flags & PB_USAGE_GPU_READ_WRITE);
assert(fenced_buf->fence);
p_atomic_inc(&fenced_buf->base.reference.count);
p_atomic_inc(&fenced_buf->base.base.reference.count);
list_del(&fenced_buf->head);
assert(fenced_mgr->num_unfenced);
@@ -275,7 +275,7 @@ fenced_buffer_remove_locked(struct fenced_manager *fenced_mgr,
list_addtail(&fenced_buf->head, &fenced_mgr->unfenced);
++fenced_mgr->num_unfenced;
if (p_atomic_dec_zero(&fenced_buf->base.reference.count)) {
if (p_atomic_dec_zero(&fenced_buf->base.base.reference.count)) {
fenced_buffer_destroy_locked(fenced_mgr, fenced_buf);
return true;
}
@@ -301,7 +301,7 @@ fenced_buffer_finish_locked(struct fenced_manager *fenced_mgr,
debug_warning("waiting for GPU");
#endif
assert(pipe_is_referenced(&fenced_buf->base.reference));
assert(pipe_is_referenced(&fenced_buf->base.base.reference));
assert(fenced_buf->fence);
if(fenced_buf->fence) {
@@ -317,7 +317,7 @@ fenced_buffer_finish_locked(struct fenced_manager *fenced_mgr,
mtx_lock(&fenced_mgr->mutex);
assert(pipe_is_referenced(&fenced_buf->base.reference));
assert(pipe_is_referenced(&fenced_buf->base.base.reference));
/*
* Only proceed if the fence object didn't change in the meanwhile.
@@ -506,7 +506,7 @@ fenced_buffer_destroy(void *winsys, struct pb_buffer *buf)
struct fenced_buffer *fenced_buf = fenced_buffer(buf);
struct fenced_manager *fenced_mgr = fenced_buf->mgr;
assert(!pipe_is_referenced(&fenced_buf->base.reference));
assert(!pipe_is_referenced(&fenced_buf->base.base.reference));
mtx_lock(&fenced_mgr->mutex);
@@ -651,7 +651,7 @@ fenced_buffer_fence(struct pb_buffer *buf,
mtx_lock(&fenced_mgr->mutex);
assert(pipe_is_referenced(&fenced_buf->base.reference));
assert(pipe_is_referenced(&fenced_buf->base.base.reference));
assert(fenced_buf->buffer);
if(fence != fenced_buf->fence) {
@@ -730,10 +730,10 @@ fenced_bufmgr_create_buffer(struct pb_manager *mgr,
if(!fenced_buf)
goto no_buffer;
pipe_reference_init(&fenced_buf->base.reference, 1);
fenced_buf->base.alignment_log2 = util_logbase2(desc->alignment);
fenced_buf->base.usage = desc->usage;
fenced_buf->base.size = size;
pipe_reference_init(&fenced_buf->base.base.reference, 1);
fenced_buf->base.base.alignment_log2 = util_logbase2(desc->alignment);
fenced_buf->base.base.usage = desc->usage;
fenced_buf->base.base.size = size;
fenced_buf->size = size;
fenced_buf->base.vtbl = &fenced_buffer_vtbl;
src/gallium/winsys/svga/drm/vmw_buffer.c
+6 -6
View File
@@ -130,7 +130,7 @@ vmw_dma_buffer_map(struct pb_buffer *_buf,
if (!buf->map)
return NULL;
if ((_buf->usage & VMW_BUFFER_USAGE_SYNC) &&
if ((_buf->base.usage & VMW_BUFFER_USAGE_SYNC) &&
!(flags & PB_USAGE_UNSYNCHRONIZED)) {
ret = vmw_ioctl_syncforcpu(buf->region,
!!(flags & PB_USAGE_DONTBLOCK),
@@ -151,7 +151,7 @@ vmw_dma_buffer_unmap(struct pb_buffer *_buf)
struct vmw_dma_buffer *buf = vmw_pb_to_dma_buffer(_buf);
enum pb_usage_flags flags = buf->map_flags;
if ((_buf->usage & VMW_BUFFER_USAGE_SYNC) &&
if ((_buf->base.usage & VMW_BUFFER_USAGE_SYNC) &&
!(flags & PB_USAGE_UNSYNCHRONIZED)) {
vmw_ioctl_releasefromcpu(buf->region,
!(flags & PB_USAGE_CPU_WRITE),
@@ -220,12 +220,12 @@ vmw_dma_bufmgr_create_buffer(struct pb_manager *_mgr,
if(!buf)
goto error1;
pipe_reference_init(&buf->base.reference, 1);
buf->base.alignment_log2 = util_logbase2(pb_desc->alignment);
buf->base.usage = pb_desc->usage & ~VMW_BUFFER_USAGE_SHARED;
pipe_reference_init(&buf->base.base.reference, 1);
buf->base.base.alignment_log2 = util_logbase2(pb_desc->alignment);
buf->base.base.usage = pb_desc->usage & ~VMW_BUFFER_USAGE_SHARED;
buf->base.vtbl = &vmw_dma_buffer_vtbl;
buf->mgr = mgr;
buf->base.size = size;
buf->base.base.size = size;
if ((pb_desc->usage & VMW_BUFFER_USAGE_SHARED) && desc->region) {
buf->region = desc->region;
} else {
src/gallium/winsys/svga/drm/vmw_context.c
+2 -2
View File
@@ -407,7 +407,7 @@ vmw_swc_region_relocation(struct svga_winsys_context *swc,
++vswc->region.staged;
if (vmw_swc_add_validate_buffer(vswc, reloc->buffer, flags)) {
vswc->seen_regions += reloc->buffer->size;
vswc->seen_regions += reloc->buffer->base.size;
if ((swc->hints & SVGA_HINT_FLAG_CAN_PRE_FLUSH) &&
vswc->seen_regions >= VMW_GMR_POOL_SIZE/5)
vswc->preemptive_flush = true;
@@ -449,7 +449,7 @@ vmw_swc_mob_relocation(struct svga_winsys_context *swc,
}
if (vmw_swc_add_validate_buffer(vswc, pb_buffer, flags)) {
vswc->seen_mobs += pb_buffer->size;
vswc->seen_mobs += pb_buffer->base.size;
if ((swc->hints & SVGA_HINT_FLAG_CAN_PRE_FLUSH) &&
vswc->seen_mobs >=