radeonsi: add SI_CPDMA_SKIP_BO_LIST_UPDATE
the next commit will use it in a clever way, because the CP DMA prefetch doesn't need this. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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@@ -133,22 +133,26 @@ static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst
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uint64_t remaining_size, unsigned user_flags,
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bool *is_first, unsigned *packet_flags)
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{
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/* Count memory usage in so that need_cs_space can take it into account. */
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r600_context_add_resource_size(&sctx->b.b, dst);
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if (src)
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r600_context_add_resource_size(&sctx->b.b, src);
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if (!(user_flags & SI_CPDMA_SKIP_BO_LIST_UPDATE)) {
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/* Count memory usage in so that need_cs_space can take it into account. */
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r600_context_add_resource_size(&sctx->b.b, dst);
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if (src)
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r600_context_add_resource_size(&sctx->b.b, src);
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}
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if (!(user_flags & SI_CPDMA_SKIP_CHECK_CS_SPACE))
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si_need_cs_space(sctx);
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/* This must be done after need_cs_space. */
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
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(struct r600_resource*)dst,
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RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
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if (src)
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if (!(user_flags & SI_CPDMA_SKIP_BO_LIST_UPDATE)) {
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
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(struct r600_resource*)src,
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RADEON_USAGE_READ, RADEON_PRIO_CP_DMA);
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(struct r600_resource*)dst,
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RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
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if (src)
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
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(struct r600_resource*)src,
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RADEON_USAGE_READ, RADEON_PRIO_CP_DMA);
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}
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/* Flush the caches for the first copy only.
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* Also wait for the previous CP DMA operations.
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@@ -372,6 +372,7 @@ void si_resource_copy_region(struct pipe_context *ctx,
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#define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
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#define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
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#define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
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#define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
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void si_copy_buffer(struct si_context *sctx,
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struct pipe_resource *dst, struct pipe_resource *src,
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