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freedreno/ir3: fixup register footprint to account for prefetch

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It is possible that the result of a pre-fs texture fetch is an output
(or partially an output) of the FS.  Sine the meta:tex_prefetch
instructions are dropped before the assembler, we need to account for
this when we fixup the register footprint.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
This commit is contained in:
Rob Clark
2019-10-11 16:15:44 -07:00
committed by Rob Clark
parent 482e1b9955
commit 392a309a55
1 changed files with 14 additions and 0 deletions
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src/freedreno/ir3/ir3_shader.c
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@@ -107,6 +107,20 @@ fixup_regfootprint(struct ir3_shader_variant *v, uint32_t gpu_id)
v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
}
}
for (i = 0; i < v->num_sampler_prefetch; i++) {
unsigned n = util_last_bit(v->sampler_prefetch[i].wrmask) - 1;
int32_t regid = v->sampler_prefetch[i].dst + n;
if (v->sampler_prefetch[i].half_precision) {
if (gpu_id < 500) {
v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
} else {
v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
}
} else {
v->info.max_reg = MAX2(v->info.max_reg, regid);
}
}
}
/* wrapper for ir3_assemble() which does some info fixup based on