aco: fix GS with no outputs

With NGG, ngg_gs_known_vtxcnt[0] would be false and ngg_gs_finale() would
assert.

With legacy GS, I don't know why the assertion was there.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7576>
This commit is contained in:
Rhys Perry
2020-11-12 14:21:00 +00:00
committed by Marge Bot
parent fdfa96561e
commit 37a2c9ace6
4 changed files with 41 additions and 9 deletions
@@ -7020,7 +7020,7 @@ void ngg_gs_write_shader_query(isel_context *ctx, nir_intrinsic_instr *instr);
void ngg_visit_set_vertex_and_primitive_count(isel_context *ctx, nir_intrinsic_instr *instr)
{
unsigned stream = nir_intrinsic_stream_id(instr);
if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
if (stream > 0 && !ctx->args->shader_info->gs.num_stream_output_components[stream])
return;
ctx->ngg_gs_known_vtxcnt[stream] = true;
@@ -7048,7 +7048,6 @@ void visit_emit_vertex_with_counter(isel_context *ctx, nir_intrinsic_instr *inst
unsigned num_components =
ctx->program->info->gs.num_stream_output_components[stream];
assert(num_components);
unsigned stride = 4u * num_components * ctx->shader->info.gs.vertices_out;
unsigned stream_offset = 0;
+10 -7
View File
@@ -479,6 +479,13 @@ void PipelineBuilder::add_stage(VkShaderStageFlagBits stage, VkShaderModule modu
owned_stages |= stage;
}
void PipelineBuilder::add_stage(VkShaderStageFlagBits stage, QoShaderModuleCreateInfo module, const char *name)
{
add_stage(stage, __qoCreateShaderModule(device, &module), name);
add_resource_decls(&module);
add_io_decls(&module);
}
void PipelineBuilder::add_vsfs(VkShaderModule vs, VkShaderModule fs)
{
add_stage(VK_SHADER_STAGE_VERTEX_BIT, vs);
@@ -487,11 +494,8 @@ void PipelineBuilder::add_vsfs(VkShaderModule vs, VkShaderModule fs)
void PipelineBuilder::add_vsfs(QoShaderModuleCreateInfo vs, QoShaderModuleCreateInfo fs)
{
add_vsfs(__qoCreateShaderModule(device, &vs), __qoCreateShaderModule(device, &fs));
add_resource_decls(&vs);
add_io_decls(&vs);
add_resource_decls(&fs);
add_io_decls(&fs);
add_stage(VK_SHADER_STAGE_VERTEX_BIT, vs);
add_stage(VK_SHADER_STAGE_FRAGMENT_BIT, fs);
}
void PipelineBuilder::add_cs(VkShaderModule cs)
@@ -501,8 +505,7 @@ void PipelineBuilder::add_cs(VkShaderModule cs)
void PipelineBuilder::add_cs(QoShaderModuleCreateInfo cs)
{
add_cs(__qoCreateShaderModule(device, &cs));
add_resource_decls(&cs);
add_stage(VK_SHADER_STAGE_COMPUTE_BIT, cs);
}
bool PipelineBuilder::is_compute() {
+1
View File
@@ -135,6 +135,7 @@ public:
void add_io_decls(QoShaderModuleCreateInfo *module);
void add_stage(VkShaderStageFlagBits stage, VkShaderModule module, const char *name="main");
void add_stage(VkShaderStageFlagBits stage, QoShaderModuleCreateInfo module, const char *name="main");
void add_vsfs(VkShaderModule vs, VkShaderModule fs);
void add_vsfs(QoShaderModuleCreateInfo vs, QoShaderModuleCreateInfo fs);
void add_cs(VkShaderModule cs);
+29
View File
@@ -78,3 +78,32 @@ BEGIN_TEST(isel.compute.simple)
pbld.print_ir(VK_SHADER_STAGE_COMPUTE_BIT, "ACO IR", true);
}
END_TEST
BEGIN_TEST(isel.gs.no_outputs)
for (unsigned i = GFX8; i <= GFX10; i++) {
if (!set_variant((chip_class)i))
continue;
QoShaderModuleCreateInfo vs = qoShaderModuleCreateInfoGLSL(VERTEX,
void main() {}
);
QoShaderModuleCreateInfo gs = qoShaderModuleCreateInfoGLSL(GEOMETRY,
layout(points) in;
layout(points, max_vertices = 1) out;
void main() {
EmitVertex();
EndPrimitive();
}
);
PipelineBuilder pbld(get_vk_device((chip_class)i));
pbld.add_stage(VK_SHADER_STAGE_VERTEX_BIT, vs);
pbld.add_stage(VK_SHADER_STAGE_GEOMETRY_BIT, gs);
pbld.create_pipeline();
//! success
fprintf(output, "success\n");
}
END_TEST