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ac/surface: initialize the FMASK slice size for GFX9+

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7924>
This commit is contained in:
Samuel Pitoiset
2020-12-04 17:40:55 +01:00
committed by Marge Bot
parent c0319e4505
commit 35964e9387
3 changed files with 4 additions and 4 deletions
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src/amd/common/ac_surface.c
+2 -1
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@@ -1404,6 +1404,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *i
surf->fmask_size = fout.fmaskBytes;
surf->fmask_alignment = fout.baseAlign;
surf->fmask_slice_size = fout.sliceSize;
surf->fmask_tile_swizzle = 0;
surf->u.legacy.fmask.slice_tile_max = (fout.pitch * fout.height) / 64;
@@ -1413,7 +1414,6 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *i
surf->u.legacy.fmask.tiling_index = fout.tileIndex;
surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight;
surf->u.legacy.fmask.pitch_in_pixels = fout.pitch;
surf->u.legacy.fmask.slice_size = fout.sliceSize;
/* Compute tile swizzle for FMASK. */
if (config->info.fmask_surf_index && !(surf->flags & RADEON_SURF_SHAREABLE)) {
@@ -1973,6 +1973,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
surf->u.gfx9.fmask.epitch = fout.pitch - 1;
surf->fmask_size = fout.fmaskBytes;
surf->fmask_alignment = fout.baseAlign;
surf->fmask_slice_size = fout.sliceSize;
/* Compute tile swizzle for the FMASK surface. */
if (config->info.fmask_surf_index && fin.swizzleMode >= ADDR_SW_64KB_Z_T &&
src/amd/common/ac_surface.h
+1 -1
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@@ -99,7 +99,6 @@ struct legacy_surf_fmask {
uint8_t tiling_index; /* max 31 */
uint8_t bankh; /* max 8 */
uint16_t pitch_in_pixels;
uint64_t slice_size;
};
struct legacy_surf_layout {
@@ -240,6 +239,7 @@ struct radeon_surf {
uint64_t fmask_size;
uint32_t surf_alignment;
uint32_t fmask_alignment;
uint64_t fmask_slice_size;
/* DCC and HTILE are very small. */
uint32_t dcc_size;
src/amd/vulkan/radv_meta_clear.c
+1 -2
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@@ -1449,8 +1449,7 @@ radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
size = image->planes[0].surface.fmask_size;
} else {
unsigned fmask_slice_size =
image->planes[0].surface.u.legacy.fmask.slice_size;
image->planes[0].surface.fmask_slice_size;
offset += fmask_slice_size * range->baseArrayLayer;
size = fmask_slice_size * radv_get_layerCount(image, range);