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i965: Update compute workgroup size limit calculation for SIMD32.

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This should have the side effect of enabling the ARB_compute_shader
extension on Gen8+ hardware and all Gen7 platforms that didn't
previously expose it (VLV and IVB GT1) due to the number of hardware
threads per subslice being insufficient in SIMD16 mode.

v2: Bump workgroup size limit for GLES too (Jordan).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
Francisco Jerez
2016-04-25 17:02:25 -07:00
parent 46ce93ed22
commit 357495b94d
1 changed files with 3 additions and 11 deletions
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src/mesa/drivers/dri/i965/brw_context.c
+3 -11
View File
@@ -709,18 +709,10 @@ static void
brw_initialize_cs_context_constants(struct brw_context *brw, unsigned max_threads)
{
struct gl_context *ctx = &brw->ctx;
/* For ES, we set these constants based on SIMD8.
*
* TODO: Once we can always generate SIMD16, we should update this.
*
* For GL, we assume we can generate a SIMD16 program, but this currently
* is not always true. This allows us to run more test cases, and will be
* required based on desktop GL compute shader requirements.
/* Maximum number of scalar compute shader invocations that can be run in
* parallel in the same subslice assuming SIMD32 dispatch.
*/
const int simd_size = ctx->API == API_OPENGL_CORE ? 16 : 8;
const uint32_t max_invocations = simd_size * max_threads;
const uint32_t max_invocations = 32 * max_threads;
ctx->Const.MaxComputeWorkGroupSize[0] = max_invocations;
ctx->Const.MaxComputeWorkGroupSize[1] = max_invocations;
ctx->Const.MaxComputeWorkGroupSize[2] = max_invocations;