anv,iris: Port the D16 workaround stalls to BLORP

Commit cd40110420 added stalls before register writes that occur when
drivers emit depth stencil packets. However, it only did so for
non-BLORP draw calls. Since those packets are sometimes emitted during
BLORP calls, add stalls there too.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4574
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10939>

src/gallium/drivers/iris/iris_blorp.c

@@ -274,6 +274,22 @@ iris_blorp_exec(struct blorp_batch *blorp_batch,
                                 PIPE_CONTROL_STALL_AT_SCOREBOARD);
 #endif
 
+#if GFX_VERx10 == 120
+   if (!(blorp_batch->flags & BLORP_BATCH_NO_EMIT_DEPTH_STENCIL)) {
+      /* Wa_14010455700
+       *
+       * ISL will change some CHICKEN registers depending on the depth surface
+       * format, along with emitting the depth and stencil packets. In that
+       * case, we want to do a depth flush and stall, so the pipeline is not
+       * using these settings while we change the registers.
+       */
+      iris_emit_end_of_pipe_sync(batch,
+                                 "Workaround: Stop pipeline for 14010455700",
+                                 PIPE_CONTROL_DEPTH_STALL |
+                                 PIPE_CONTROL_DEPTH_CACHE_FLUSH);
+   }
+#endif
+
    /* Flush the render cache in cases where the same surface is used with
     * different aux modes, which can lead to GPU hangs.  Invalidation of
     * sampler caches and flushing of any caches which had previously written

src/intel/vulkan/genX_blorp_exec.c

@@ -243,6 +243,22 @@ genX(blorp_exec)(struct blorp_batch *batch,
       ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
 #endif
 
+#if GFX_VERx10 == 120
+   if (!(batch->flags & BLORP_BATCH_NO_EMIT_DEPTH_STENCIL)) {
+      /* Wa_14010455700
+       *
+       * ISL will change some CHICKEN registers depending on the depth surface
+       * format, along with emitting the depth and stencil packets. In that
+       * case, we want to do a depth flush and stall, so the pipeline is not
+       * using these settings while we change the registers.
+       */
+      cmd_buffer->state.pending_pipe_bits |=
+         ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |
+         ANV_PIPE_DEPTH_STALL_BIT |
+         ANV_PIPE_END_OF_PIPE_SYNC_BIT;
+   }
+#endif
+
 #if GFX_VER == 7
    /* The MI_LOAD/STORE_REGISTER_MEM commands which BLORP uses to implement
     * indirect fast-clear colors can cause GPU hangs if we don't stall first.