iris: Support up to 128 textures

This is required for OpenCL.  I kind-of hate this patch.  I really don't
like GROUP_TEXTURE_LOW64 and GROUP_TEXTURE_HIGH64 but it was either that
or I had to make all the used bitsets 128 which would have mean making
them BITSET and that would have been a lot more churn.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16442>
This commit is contained in:
Jason Ekstrand
2022-04-15 17:01:17 -05:00
committed by Marge Bot
parent 06a0de492a
commit 3417a0c4a2
5 changed files with 47 additions and 19 deletions
+3 -2
View File
@@ -452,7 +452,8 @@ enum iris_surface_group {
IRIS_SURFACE_GROUP_RENDER_TARGET,
IRIS_SURFACE_GROUP_RENDER_TARGET_READ,
IRIS_SURFACE_GROUP_CS_WORK_GROUPS,
IRIS_SURFACE_GROUP_TEXTURE,
IRIS_SURFACE_GROUP_TEXTURE_LOW64,
IRIS_SURFACE_GROUP_TEXTURE_HIGH64,
IRIS_SURFACE_GROUP_IMAGE,
IRIS_SURFACE_GROUP_UBO,
IRIS_SURFACE_GROUP_SSBO,
@@ -569,7 +570,7 @@ struct iris_shader_state {
uint64_t bound_image_views;
/** Bitfield of which sampler views are bound (non-null). */
uint32_t bound_sampler_views;
BITSET_DECLARE(bound_sampler_views, IRIS_MAX_TEXTURES);
/** Bitfield of which shader storage buffers are bound (non-null). */
uint32_t bound_ssbos;
+20 -6
View File
@@ -737,7 +737,8 @@ static const char *surface_group_names[] = {
[IRIS_SURFACE_GROUP_RENDER_TARGET] = "render target",
[IRIS_SURFACE_GROUP_RENDER_TARGET_READ] = "non-coherent render target read",
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS] = "CS work groups",
[IRIS_SURFACE_GROUP_TEXTURE] = "texture",
[IRIS_SURFACE_GROUP_TEXTURE_LOW64] = "texture",
[IRIS_SURFACE_GROUP_TEXTURE_HIGH64] = "texture",
[IRIS_SURFACE_GROUP_UBO] = "ubo",
[IRIS_SURFACE_GROUP_SSBO] = "ssbo",
[IRIS_SURFACE_GROUP_IMAGE] = "image",
@@ -914,8 +915,15 @@ iris_setup_binding_table(const struct intel_device_info *devinfo,
bt->sizes[IRIS_SURFACE_GROUP_CS_WORK_GROUPS] = 1;
}
bt->sizes[IRIS_SURFACE_GROUP_TEXTURE] = BITSET_LAST_BIT(info->textures_used);
bt->used_mask[IRIS_SURFACE_GROUP_TEXTURE] = info->textures_used[0];
assert(ARRAY_SIZE(info->textures_used) >= 4);
int max_tex = BITSET_LAST_BIT(info->textures_used);
assert(max_tex <= 128);
bt->sizes[IRIS_SURFACE_GROUP_TEXTURE_LOW64] = MIN2(64, max_tex);
bt->sizes[IRIS_SURFACE_GROUP_TEXTURE_HIGH64] = MAX2(0, max_tex - 64);
bt->used_mask[IRIS_SURFACE_GROUP_TEXTURE_LOW64] =
info->textures_used[0] | ((uint64_t)info->textures_used[1]) << 32;
bt->used_mask[IRIS_SURFACE_GROUP_TEXTURE_HIGH64] =
info->textures_used[2] | ((uint64_t)info->textures_used[3]) << 32;
bt->sizes[IRIS_SURFACE_GROUP_IMAGE] = info->num_images;
@@ -1039,9 +1047,15 @@ iris_setup_binding_table(const struct intel_device_info *devinfo,
nir_foreach_instr (instr, block) {
if (instr->type == nir_instr_type_tex) {
nir_tex_instr *tex = nir_instr_as_tex(instr);
tex->texture_index =
iris_group_index_to_bti(bt, IRIS_SURFACE_GROUP_TEXTURE,
tex->texture_index);
if (tex->texture_index < 64) {
tex->texture_index =
iris_group_index_to_bti(bt, IRIS_SURFACE_GROUP_TEXTURE_LOW64,
tex->texture_index);
} else {
tex->texture_index =
iris_group_index_to_bti(bt, IRIS_SURFACE_GROUP_TEXTURE_HIGH64,
tex->texture_index - 64);
}
continue;
}
+7 -3
View File
@@ -89,10 +89,14 @@ resolve_sampler_views(struct iris_context *ice,
bool *draw_aux_buffer_disabled,
bool consider_framebuffer)
{
uint32_t views = info ? (shs->bound_sampler_views & info->textures_used[0]) : 0;
if (info == NULL)
return;
int i;
BITSET_FOREACH_SET(i, shs->bound_sampler_views, IRIS_MAX_TEXTURES) {
if (!BITSET_TEST(info->textures_used, i))
continue;
while (views) {
const int i = u_bit_scan(&views);
struct iris_sampler_view *isv = shs->textures[i];
if (isv->res->base.b.target != PIPE_BUFFER) {
+1 -1
View File
@@ -50,7 +50,7 @@ struct u_trace;
#define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
#define WRITE_ONCE(x, v) *(volatile __typeof__(x) *)&(x) = (v)
#define IRIS_MAX_TEXTURES 32
#define IRIS_MAX_TEXTURES 128
#define IRIS_MAX_SAMPLERS 32
#define IRIS_MAX_IMAGES 64
#define IRIS_MAX_SOL_BUFFERS 4
+16 -7
View File
@@ -2959,8 +2959,11 @@ iris_set_sampler_views(struct pipe_context *ctx,
struct iris_shader_state *shs = &ice->state.shaders[stage];
unsigned i;
shs->bound_sampler_views &=
~u_bit_consecutive(start, count + unbind_num_trailing_slots);
if (count == 0 && unbind_num_trailing_slots == 0)
return;
BITSET_CLEAR_RANGE(shs->bound_sampler_views, start,
start + count + unbind_num_trailing_slots - 1);
for (i = 0; i < count; i++) {
struct pipe_sampler_view *pview = views ? views[i] : NULL;
@@ -2984,7 +2987,7 @@ iris_set_sampler_views(struct pipe_context *ctx,
view->res->bind_history |= PIPE_BIND_SAMPLER_VIEW;
view->res->bind_stages |= 1 << stage;
shs->bound_sampler_views |= 1 << (start + i);
BITSET_SET(shs->bound_sampler_views, start + i);
update_surface_state_addrs(ice->state.surface_uploader,
&view->surface_state, view->res->bo);
@@ -5150,13 +5153,20 @@ iris_populate_binding_table(struct iris_context *ice,
}
}
foreach_surface_used(i, IRIS_SURFACE_GROUP_TEXTURE) {
foreach_surface_used(i, IRIS_SURFACE_GROUP_TEXTURE_LOW64) {
struct iris_sampler_view *view = shs->textures[i];
uint32_t addr = view ? use_sampler_view(ice, batch, view)
: use_null_surface(batch, ice);
push_bt_entry(addr);
}
foreach_surface_used(i, IRIS_SURFACE_GROUP_TEXTURE_HIGH64) {
struct iris_sampler_view *view = shs->textures[64 + i];
uint32_t addr = view ? use_sampler_view(ice, batch, view)
: use_null_surface(batch, ice);
push_bt_entry(addr);
}
foreach_surface_used(i, IRIS_SURFACE_GROUP_IMAGE) {
uint32_t addr = use_image(batch, ice, shs, info, i);
push_bt_entry(addr);
@@ -7569,9 +7579,8 @@ iris_rebind_buffer(struct iris_context *ice,
}
if (res->bind_history & PIPE_BIND_SAMPLER_VIEW) {
uint32_t bound_sampler_views = shs->bound_sampler_views;
while (bound_sampler_views) {
const int i = u_bit_scan(&bound_sampler_views);
int i;
BITSET_FOREACH_SET(i, shs->bound_sampler_views, IRIS_MAX_TEXTURES) {
struct iris_sampler_view *isv = shs->textures[i];
struct iris_bo *bo = isv->res->bo;