iris: Support up to 128 textures
This is required for OpenCL. I kind-of hate this patch. I really don't like GROUP_TEXTURE_LOW64 and GROUP_TEXTURE_HIGH64 but it was either that or I had to make all the used bitsets 128 which would have mean making them BITSET and that would have been a lot more churn. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16442>
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@@ -452,7 +452,8 @@ enum iris_surface_group {
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IRIS_SURFACE_GROUP_RENDER_TARGET,
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IRIS_SURFACE_GROUP_RENDER_TARGET_READ,
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IRIS_SURFACE_GROUP_CS_WORK_GROUPS,
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IRIS_SURFACE_GROUP_TEXTURE,
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IRIS_SURFACE_GROUP_TEXTURE_LOW64,
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IRIS_SURFACE_GROUP_TEXTURE_HIGH64,
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IRIS_SURFACE_GROUP_IMAGE,
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IRIS_SURFACE_GROUP_UBO,
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IRIS_SURFACE_GROUP_SSBO,
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@@ -569,7 +570,7 @@ struct iris_shader_state {
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uint64_t bound_image_views;
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/** Bitfield of which sampler views are bound (non-null). */
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uint32_t bound_sampler_views;
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BITSET_DECLARE(bound_sampler_views, IRIS_MAX_TEXTURES);
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/** Bitfield of which shader storage buffers are bound (non-null). */
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uint32_t bound_ssbos;
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@@ -737,7 +737,8 @@ static const char *surface_group_names[] = {
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[IRIS_SURFACE_GROUP_RENDER_TARGET] = "render target",
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[IRIS_SURFACE_GROUP_RENDER_TARGET_READ] = "non-coherent render target read",
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[IRIS_SURFACE_GROUP_CS_WORK_GROUPS] = "CS work groups",
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[IRIS_SURFACE_GROUP_TEXTURE] = "texture",
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[IRIS_SURFACE_GROUP_TEXTURE_LOW64] = "texture",
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[IRIS_SURFACE_GROUP_TEXTURE_HIGH64] = "texture",
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[IRIS_SURFACE_GROUP_UBO] = "ubo",
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[IRIS_SURFACE_GROUP_SSBO] = "ssbo",
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[IRIS_SURFACE_GROUP_IMAGE] = "image",
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@@ -914,8 +915,15 @@ iris_setup_binding_table(const struct intel_device_info *devinfo,
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bt->sizes[IRIS_SURFACE_GROUP_CS_WORK_GROUPS] = 1;
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}
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bt->sizes[IRIS_SURFACE_GROUP_TEXTURE] = BITSET_LAST_BIT(info->textures_used);
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bt->used_mask[IRIS_SURFACE_GROUP_TEXTURE] = info->textures_used[0];
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assert(ARRAY_SIZE(info->textures_used) >= 4);
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int max_tex = BITSET_LAST_BIT(info->textures_used);
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assert(max_tex <= 128);
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bt->sizes[IRIS_SURFACE_GROUP_TEXTURE_LOW64] = MIN2(64, max_tex);
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bt->sizes[IRIS_SURFACE_GROUP_TEXTURE_HIGH64] = MAX2(0, max_tex - 64);
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bt->used_mask[IRIS_SURFACE_GROUP_TEXTURE_LOW64] =
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info->textures_used[0] | ((uint64_t)info->textures_used[1]) << 32;
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bt->used_mask[IRIS_SURFACE_GROUP_TEXTURE_HIGH64] =
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info->textures_used[2] | ((uint64_t)info->textures_used[3]) << 32;
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bt->sizes[IRIS_SURFACE_GROUP_IMAGE] = info->num_images;
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@@ -1039,9 +1047,15 @@ iris_setup_binding_table(const struct intel_device_info *devinfo,
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nir_foreach_instr (instr, block) {
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if (instr->type == nir_instr_type_tex) {
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nir_tex_instr *tex = nir_instr_as_tex(instr);
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tex->texture_index =
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iris_group_index_to_bti(bt, IRIS_SURFACE_GROUP_TEXTURE,
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tex->texture_index);
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if (tex->texture_index < 64) {
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tex->texture_index =
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iris_group_index_to_bti(bt, IRIS_SURFACE_GROUP_TEXTURE_LOW64,
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tex->texture_index);
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} else {
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tex->texture_index =
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iris_group_index_to_bti(bt, IRIS_SURFACE_GROUP_TEXTURE_HIGH64,
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tex->texture_index - 64);
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}
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continue;
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}
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@@ -89,10 +89,14 @@ resolve_sampler_views(struct iris_context *ice,
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bool *draw_aux_buffer_disabled,
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bool consider_framebuffer)
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{
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uint32_t views = info ? (shs->bound_sampler_views & info->textures_used[0]) : 0;
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if (info == NULL)
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return;
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int i;
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BITSET_FOREACH_SET(i, shs->bound_sampler_views, IRIS_MAX_TEXTURES) {
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if (!BITSET_TEST(info->textures_used, i))
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continue;
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while (views) {
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const int i = u_bit_scan(&views);
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struct iris_sampler_view *isv = shs->textures[i];
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if (isv->res->base.b.target != PIPE_BUFFER) {
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@@ -50,7 +50,7 @@ struct u_trace;
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#define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
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#define WRITE_ONCE(x, v) *(volatile __typeof__(x) *)&(x) = (v)
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#define IRIS_MAX_TEXTURES 32
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#define IRIS_MAX_TEXTURES 128
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#define IRIS_MAX_SAMPLERS 32
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#define IRIS_MAX_IMAGES 64
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#define IRIS_MAX_SOL_BUFFERS 4
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@@ -2959,8 +2959,11 @@ iris_set_sampler_views(struct pipe_context *ctx,
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struct iris_shader_state *shs = &ice->state.shaders[stage];
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unsigned i;
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shs->bound_sampler_views &=
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~u_bit_consecutive(start, count + unbind_num_trailing_slots);
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if (count == 0 && unbind_num_trailing_slots == 0)
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return;
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BITSET_CLEAR_RANGE(shs->bound_sampler_views, start,
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start + count + unbind_num_trailing_slots - 1);
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for (i = 0; i < count; i++) {
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struct pipe_sampler_view *pview = views ? views[i] : NULL;
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@@ -2984,7 +2987,7 @@ iris_set_sampler_views(struct pipe_context *ctx,
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view->res->bind_history |= PIPE_BIND_SAMPLER_VIEW;
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view->res->bind_stages |= 1 << stage;
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shs->bound_sampler_views |= 1 << (start + i);
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BITSET_SET(shs->bound_sampler_views, start + i);
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update_surface_state_addrs(ice->state.surface_uploader,
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&view->surface_state, view->res->bo);
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@@ -5150,13 +5153,20 @@ iris_populate_binding_table(struct iris_context *ice,
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}
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}
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foreach_surface_used(i, IRIS_SURFACE_GROUP_TEXTURE) {
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foreach_surface_used(i, IRIS_SURFACE_GROUP_TEXTURE_LOW64) {
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struct iris_sampler_view *view = shs->textures[i];
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uint32_t addr = view ? use_sampler_view(ice, batch, view)
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: use_null_surface(batch, ice);
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push_bt_entry(addr);
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}
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foreach_surface_used(i, IRIS_SURFACE_GROUP_TEXTURE_HIGH64) {
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struct iris_sampler_view *view = shs->textures[64 + i];
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uint32_t addr = view ? use_sampler_view(ice, batch, view)
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: use_null_surface(batch, ice);
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push_bt_entry(addr);
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}
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foreach_surface_used(i, IRIS_SURFACE_GROUP_IMAGE) {
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uint32_t addr = use_image(batch, ice, shs, info, i);
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push_bt_entry(addr);
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@@ -7569,9 +7579,8 @@ iris_rebind_buffer(struct iris_context *ice,
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}
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if (res->bind_history & PIPE_BIND_SAMPLER_VIEW) {
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uint32_t bound_sampler_views = shs->bound_sampler_views;
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while (bound_sampler_views) {
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const int i = u_bit_scan(&bound_sampler_views);
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int i;
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BITSET_FOREACH_SET(i, shs->bound_sampler_views, IRIS_MAX_TEXTURES) {
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struct iris_sampler_view *isv = shs->textures[i];
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struct iris_bo *bo = isv->res->bo;
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