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radeonsi: tune NGG shader culling vertex threshold for each chip

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These are based on my testing and estimation.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8434>
This commit is contained in:
Marek Olšák
2021-01-14 08:53:52 -05:00
committed by Marge Bot
parent ffbf3a5f8b
commit 34114e1dcb
1 changed files with 18 additions and 2 deletions
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src/gallium/drivers/radeonsi/si_state_shaders.c
+18 -2
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@@ -2806,8 +2806,24 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
else if (sscreen->options.shader_culling ||
sscreen->info.chip_class == GFX10_3 ||
(sscreen->info.chip_class == GFX10 &&
sscreen->info.is_pro_graphics))
sel->ngg_cull_vert_threshold = 1500; /* vertex count must be more than this */
sscreen->info.is_pro_graphics)) {
/* Rough estimates. */
switch (sctx->family) {
case CHIP_NAVI10:
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
sel->ngg_cull_vert_threshold = 511;
break;
case CHIP_NAVI14:
case CHIP_NAVY_FLOUNDER:
case CHIP_DIMGREY_CAVEFISH:
case CHIP_VANGOGH:
sel->ngg_cull_vert_threshold = 255;
break;
default:
assert(!sscreen->use_ngg_culling);
}
}
} else if (sel->info.stage == MESA_SHADER_TESS_EVAL) {
if (sel->rast_prim == PIPE_PRIM_TRIANGLES &&
(sscreen->debug_flags & DBG(ALWAYS_NGG_CULLING_ALL) ||