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radeonsi: add si_screen::has_ls_vgpr_init_bug

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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
2017-11-07 03:52:34 +01:00
parent cde664ab81
commit 33000e7c43
4 changed files with 5 additions and 3 deletions
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src/gallium/drivers/radeonsi/si_pipe.c
+2
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@@ -1074,6 +1074,8 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
sscreen->b.family <= CHIP_POLARIS12) ||
sscreen->b.family == CHIP_VEGA10 ||
sscreen->b.family == CHIP_RAVEN;
sscreen->has_ls_vgpr_init_bug = sscreen->b.family == CHIP_VEGA10 ||
sscreen->b.family == CHIP_RAVEN;
if (sscreen->b.debug_flags & DBG(DPBB)) {
sscreen->dpbb_allowed = true;
src/gallium/drivers/radeonsi/si_pipe.h
+1
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@@ -97,6 +97,7 @@ struct si_screen {
bool commutative_blend_add;
bool clear_db_cache_before_clear;
bool has_msaa_sample_loc_bug;
bool has_ls_vgpr_init_bug;
bool dpbb_allowed;
bool dfsm_allowed;
bool llvm_has_working_vgpr_indexing;
src/gallium/drivers/radeonsi/si_shader.c
+1 -2
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@@ -6882,8 +6882,7 @@ static void si_build_vs_prolog_function(struct si_shader_context *ctx,
si_init_exec_from_input(ctx, 3, 0);
if (key->vs_prolog.as_ls &&
(ctx->screen->b.family == CHIP_VEGA10 ||
ctx->screen->b.family == CHIP_RAVEN)) {
ctx->screen->has_ls_vgpr_init_bug) {
/* If there are no HS threads, SPI loads the LS VGPRs
* starting at VGPR 0. Shift them back to where they
* belong.
src/gallium/drivers/radeonsi/si_state_draw.c
+1 -1
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@@ -1282,7 +1282,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
}
if (sctx->tes_shader.cso &&
(sctx->b.family == CHIP_VEGA10 || sctx->b.family == CHIP_RAVEN)) {
sctx->screen->has_ls_vgpr_init_bug) {
/* Determine whether the LS VGPR fix should be applied.
*
* It is only required when num input CPs > num output CPs,