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radv: fix emitting VS prologs for merged shaders compiled separately on GFX10+

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RSRC1 isn't equal to the VS RSRC1 and both config registers need to
be re-emitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27574>
This commit is contained in:
Samuel Pitoiset
2024-02-12 14:05:39 +01:00
committed by Marge Bot
parent 6762307698
commit 32c1e45718
1 changed files with 1 additions and 1 deletions
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src/amd/vulkan/radv_cmd_buffer.c
+1 -1
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@@ -3967,7 +3967,7 @@ emit_prolog_regs(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *v
radeon_set_sh_reg(cmd_buffer->cs, pgm_lo_reg, prolog->va >> 8);
if (chip < GFX10) {
if (chip < GFX10 || vs_shader->info.merged_shader_compiled_separately) {
radeon_set_sh_reg(cmd_buffer->cs, rsrc1_reg, rsrc1);
if (vs_shader->info.merged_shader_compiled_separately) {