i965: CS writes/reads should use I915_GEM_INSTRUCTION
Otherwise the gen6 w/a in the kernel won't kick in and the write will land nowhere. Inspired by a patch Ken pointed me at which had the same issue (but isn't yet merged and also for a gen7+ feature). An audit of the entire driver didn't reveal any other case than the one in in the write_reg helper used by the gen6 queryobj code. Acked-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Tested-by: Xinkai Chen <yeled.nova@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Cc: "9.2" <mesa-stable@lists.freedesktop.org>
This commit is contained in:
committed by
Kenneth Graunke
parent
f278d49c4b
commit
32a3f5f6d7
@@ -115,14 +115,14 @@ brw_store_register_mem64(struct brw_context *brw,
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BEGIN_BATCH(3);
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OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
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OUT_BATCH(reg);
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OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
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OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
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idx * sizeof(uint64_t));
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ADVANCE_BATCH();
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BEGIN_BATCH(3);
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OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
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OUT_BATCH(reg + sizeof(uint32_t));
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OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
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OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
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sizeof(uint32_t) + idx * sizeof(uint64_t));
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ADVANCE_BATCH();
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}
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