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intel/fs: Fix Gen7 compressed source region alignment restriction for SIMD32

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Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Francisco Jerez
2017-01-13 17:04:23 -08:00
committed by Jason Ekstrand
parent 6909aed90e
commit 2fd0aed89a
1 changed files with 7 additions and 1 deletions
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src/intel/compiler/brw_fs.cpp
+7 -1
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@@ -5076,8 +5076,14 @@ get_fpu_lowered_simd_width(const struct gen_device_info *devinfo,
type_sz(inst->dst.type) == 4 && inst->dst.stride == 1 &&
type_sz(inst->src[i].type) == 2 && inst->src[i].stride == 1;
/* We check size_read(i) against size_written instead of REG_SIZE
* because we want to properly handle SIMD32. In SIMD32, you can end
* up with writes to 4 registers and a source that reads 2 registers
* and we may still need to lower all the way to SIMD8 in that case.
*/
if (inst->size_written > REG_SIZE &&
inst->size_read(i) != 0 && inst->size_read(i) <= REG_SIZE &&
inst->size_read(i) != 0 &&
inst->size_read(i) < inst->size_written &&
!is_scalar_exception && !is_packed_word_exception) {
const unsigned reg_count = DIV_ROUND_UP(inst->size_written, REG_SIZE);
max_width = MIN2(max_width, inst->exec_size / reg_count);